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Date: Thu, 1 Nov 2018 20:43:34 +0100
From: Wolfram Sang <wsa@the-dreams.de>
To: Niklas =?utf-8?Q?S=C3=B6derlund?= <niklas.soderlund@ragnatech.se>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>,
        Wolfram Sang <wsa+renesas@sang-engineering.com>,
        linux-renesas-soc@vger.kernel.org,
        Niklas =?utf-8?Q?S=C3=B6derlund?=
        <niklas.soderlund+renesas@ragnatech.se>
Subject: Re: [PATCH 0/2] renesas: rcar-gen3: add HS400 quirk for SD clock
Message-ID: <20181101194332.GR2433@kunai>
References: <20181031232518.2490-1-niklas.soderlund@ragnatech.se>
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> This is the result of the SDHI hackathon for a possible solution to the=
=20
> clock issue on early ES versions. It is based on the Gen2 solution where=
=20
> a row of the possible clock settings are ignored on the effected SoC+ES=
=20
> versions. The first row is not effected when reading settings left by=20
> the bootloader, only when the setting the clock.

We really thought about exposing both clocks, SDn and SDHn. I got
convinced to use this less intrusive approach to get HS400 reliably to
work as a first step. "First make it work, then make it beautiful" so to
say...


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