From: Pavel Machek <pavel@ucw.cz>
To: Lubomir Rintel <lkundrak@v3.sk>
Cc: linux-kernel@vger.kernel.org,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <marc.zyngier@arm.com>
Subject: Re: [PATCH] irqchip/mmp: only touch the PJ4 & FIQ bits on enable/disable
Date: Fri, 2 Nov 2018 23:16:34 +0100 [thread overview]
Message-ID: <20181102221634.GD5322@amd> (raw)
In-Reply-To: <20180910120425.164416-1-lkundrak@v3.sk>
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On Mon 2018-09-10 14:04:25, Lubomir Rintel wrote:
> On an OLPC XO 1.75 machine, the "security processor" handles the GPIO 71
> and 72 interrupts. Don't reset the "route to SP" bit (4).
>
> I'm just assuming the bit 4 is the "route to SP" bit -- it fixes the
> SP-based keyboard for me and <mach-mmp/regs-icu.h> defines
> ICU_INT_ROUTE_SP_IRQ to be 1 << 4. When asked for a data sheet, Marvell
> told me to fuck off, politely.
"Marvell was not exactly helpful".
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Pavel Machek <pavel@ucw.cz>
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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prev parent reply other threads:[~2018-11-02 22:16 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-10 12:04 [PATCH] irqchip/mmp: only touch the PJ4 & FIQ bits on enable/disable Lubomir Rintel
2018-11-02 22:16 ` Pavel Machek [this message]
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