diff for duplicates of <20181103121606.2fc461ec@archlinux> diff --git a/a/1.txt b/N1/1.txt index 3eb30d5..4cdbd1e 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -3,23 +3,21 @@ Stefan Popa <stefan.popa@analog.com> wrote: > The ad7124-4 and ad7124-8 are a family of 4 and 8 channel sigma-delta ADCs > with 24-bit precision and reference. ->=20 +> > Three power modes are available which in turn affect the output data rate: > * Full power: 9.38 SPS to 19,200 SPS > * Mid power: 2.34 SPS to 4800 SPS > * Low power: 1.17 SPS to 2400 SPS ->=20 +> > The ad7124-4 can be configured to have four differential inputs, while > ad7124-8 can have 8. Moreover, ad7124 also supports per channel > configuration. Each configuration consists of gain, reference source, > output data rate and bipolar/unipolar configuration. ->=20 +> > Datasheets: -> Link: http://www.analog.com/media/en/technical-documentation/data-sheets/= -AD7124-4.pdf -> Link: http://www.analog.com/media/en/technical-documentation/data-sheets/= -ad7124-8.pdf ->=20 +> Link: http://www.analog.com/media/en/technical-documentation/data-sheets/AD7124-4.pdf +> Link: http://www.analog.com/media/en/technical-documentation/data-sheets/ad7124-8.pdf +> > Signed-off-by: Stefan Popa <stefan.popa@analog.com> Hi Stefan, @@ -46,25 +44,20 @@ Jonathan > - Removed channel, address, scan_index and shift fields from > ad7124_channel_template. > - Added a sanity check for val2 in ad7124_write_raw(). -> - Used the "reg" property to get the channel address and "adi,diff-chann= -els" -> for the differential pins. The "adi,channel-number" property was remov= -ed. -> - When calling regulator_get_optional, the probe is given up in case of = -error, +> - Used the "reg" property to get the channel address and "adi,diff-channels" +> for the differential pins. The "adi,channel-number" property was removed. +> - When calling regulator_get_optional, the probe is given up in case of error, > but continues in case of -ENODEV. -> - clk_disable_unprepare() is called before ad_sd_cleanup_buffer_and_trig= -ger +> - clk_disable_unprepare() is called before ad_sd_cleanup_buffer_and_trigger > in ad7124_remove(). ->=20 +> > MAINTAINERS | 7 + > drivers/iio/adc/Kconfig | 11 + > drivers/iio/adc/Makefile | 1 + -> drivers/iio/adc/ad7124.c | 648 +++++++++++++++++++++++++++++++++++++++++= -++++++ +> drivers/iio/adc/ad7124.c | 648 +++++++++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 667 insertions(+) > create mode 100644 drivers/iio/adc/ad7124.c ->=20 +> > diff --git a/MAINTAINERS b/MAINTAINERS > index f642044..3a1bfcb 100644 > --- a/MAINTAINERS @@ -72,7 +65,7 @@ ger > @@ -839,6 +839,13 @@ S: Supported > F: drivers/iio/dac/ad5758.c > F: Documentation/devicetree/bindings/iio/dac/ad5758.txt -> =20 +> > +ANALOG DEVICES INC AD7124 DRIVER > +M: Stefan Popa <stefan.popa@analog.com> > +L: linux-iio@vger.kernel.org @@ -90,7 +83,7 @@ ger > @@ -10,6 +10,17 @@ config AD_SIGMA_DELTA > select IIO_BUFFER > select IIO_TRIGGERED_BUFFER -> =20 +> > +config AD7124 > + tristate "Analog Devices AD7124 and similar sigma-delta ADCs driver" > + depends on SPI_MASTER @@ -110,13 +103,13 @@ ger > --- a/drivers/iio/adc/Makefile > +++ b/drivers/iio/adc/Makefile > @@ -5,6 +5,7 @@ -> =20 +> > # When adding new entries keep the list in alphabetical order -> obj-$(CONFIG_AD_SIGMA_DELTA) +=3D ad_sigma_delta.o -> +obj-$(CONFIG_AD7124) +=3D ad7124.o -> obj-$(CONFIG_AD7266) +=3D ad7266.o -> obj-$(CONFIG_AD7291) +=3D ad7291.o -> obj-$(CONFIG_AD7298) +=3D ad7298.o +> obj-$(CONFIG_AD_SIGMA_DELTA) += ad_sigma_delta.o +> +obj-$(CONFIG_AD7124) += ad7124.o +> obj-$(CONFIG_AD7266) += ad7266.o +> obj-$(CONFIG_AD7291) += ad7291.o +> obj-$(CONFIG_AD7298) += ad7298.o > diff --git a/drivers/iio/adc/ad7124.c b/drivers/iio/adc/ad7124.c > new file mode 100644 > index 0000000..0660135 @@ -209,21 +202,21 @@ ger > + AD7124_FULL_POWER, > +}; > + -> +static const unsigned int ad7124_gain[8] =3D { +> +static const unsigned int ad7124_gain[8] = { > + 1, 2, 4, 8, 16, 32, 64, 128 > +}; > + -> +static const int ad7124_master_clk_freq_hz[3] =3D { -> + [AD7124_LOW_POWER] =3D 76800, -> + [AD7124_MID_POWER] =3D 153600, -> + [AD7124_FULL_POWER] =3D 614400, +> +static const int ad7124_master_clk_freq_hz[3] = { +> + [AD7124_LOW_POWER] = 76800, +> + [AD7124_MID_POWER] = 153600, +> + [AD7124_FULL_POWER] = 614400, > +}; > + -> +static const char * const ad7124_ref_names[] =3D { -> + [AD7124_REFIN1] =3D "refin1", -> + [AD7124_REFIN2] =3D "refin2", -> + [AD7124_INT_REF] =3D "int", -> + [AD7124_AVDD_REF] =3D "avdd", +> +static const char * const ad7124_ref_names[] = { +> + [AD7124_REFIN1] = "refin1", +> + [AD7124_REFIN2] = "refin2", +> + [AD7124_INT_REF] = "int", +> + [AD7124_AVDD_REF] = "avdd", > +}; > + > +struct ad7124_chip_info { @@ -249,27 +242,27 @@ ger > + unsigned int num_channels; > +}; > + -> +static const struct iio_chan_spec ad7124_channel_template =3D { -> + .type =3D IIO_VOLTAGE, -> + .indexed =3D 1, -> + .differential =3D 1, -> + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | +> +static const struct iio_chan_spec ad7124_channel_template = { +> + .type = IIO_VOLTAGE, +> + .indexed = 1, +> + .differential = 1, +> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | > + BIT(IIO_CHAN_INFO_SCALE) | > + BIT(IIO_CHAN_INFO_OFFSET) | > + BIT(IIO_CHAN_INFO_SAMP_FREQ), -> + .scan_type =3D { -> + .sign =3D 'u', -> + .realbits =3D 24, -> + .storagebits =3D 32, +> + .scan_type = { +> + .sign = 'u', +> + .realbits = 24, +> + .storagebits = 32, > + }, > +}; > + -> +static struct ad7124_chip_info ad7124_chip_info_tbl[] =3D { -> + [ID_AD7124_4] =3D { -> + .num_inputs =3D 8, +> +static struct ad7124_chip_info ad7124_chip_info_tbl[] = { +> + [ID_AD7124_4] = { +> + .num_inputs = 8, > + }, -> + [ID_AD7124_8] =3D { -> + .num_inputs =3D 16, +> + [ID_AD7124_8] = { +> + .num_inputs = 16, > + }, > +}; > + @@ -278,8 +271,8 @@ ger > +{ > + int i; > + -> + for (i =3D 0; i < size; i++) { -> + if (val <=3D array[i]) +> + for (i = 0; i < size; i++) { +> + if (val <= array[i]) > + return i; > + } > + @@ -295,12 +288,12 @@ ger > + unsigned int readval; > + int ret; > + -> + ret =3D ad_sd_read_reg(&st->sd, addr, bytes, &readval); +> + ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval); > + if (ret < 0) > + return ret; > + -> + readval &=3D ~mask; -> + readval |=3D val; +> + readval &= ~mask; +> + readval |= val; > + > + return ad_sd_write_reg(&st->sd, addr, bytes, readval); > +} @@ -308,33 +301,32 @@ ger > +static int ad7124_set_mode(struct ad_sigma_delta *sd, > + enum ad_sigma_delta_mode mode) > +{ -> + struct ad7124_state *st =3D container_of(sd, struct ad7124_state, sd); +> + struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); > + -> + st->adc_control &=3D ~AD7124_ADC_CTRL_MODE_MSK; -> + st->adc_control |=3D AD7124_ADC_CTRL_MODE(mode); +> + st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK; +> + st->adc_control |= AD7124_ADC_CTRL_MODE(mode); > + > + return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control); > +} > + -> +static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int ch= -annel) +> +static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel) > +{ -> + struct ad7124_state *st =3D container_of(sd, struct ad7124_state, sd); +> + struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); > + unsigned int val; > + -> + val =3D st->channel_config[channel].ain | AD7124_CHANNEL_EN(1) | +> + val = st->channel_config[channel].ain | AD7124_CHANNEL_EN(1) | > + AD7124_CHANNEL_SETUP(channel); > + > + return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(channel), 2, val); > +} > + -> +static const struct ad_sigma_delta_info ad7124_sigma_delta_info =3D { -> + .set_channel =3D ad7124_set_channel, -> + .set_mode =3D ad7124_set_mode, -> + .has_registers =3D true, -> + .addr_shift =3D 0, -> + .read_mask =3D BIT(6), -> + .data_reg =3D AD7124_DATA, +> +static const struct ad_sigma_delta_info ad7124_sigma_delta_info = { +> + .set_channel = ad7124_set_channel, +> + .set_mode = ad7124_set_mode, +> + .has_registers = true, +> + .addr_shift = 0, +> + .read_mask = BIT(6), +> + .data_reg = AD7124_DATA, > +}; > + > +static int ad7124_set_channel_odr(struct ad7124_state *st, @@ -344,27 +336,27 @@ annel) > + unsigned int fclk, odr_sel_bits; > + int ret; > + -> + fclk =3D clk_get_rate(st->mclk); +> + fclk = clk_get_rate(st->mclk); > + /* -> + * FS[10:0] =3D fCLK / (fADC x 32) where: +> + * FS[10:0] = fCLK / (fADC x 32) where: > + * fADC is the output data rate > + * fCLK is the master clock frequency > + * FS[10:0] are the bits in the filter register > + * FS[10:0] can have a value from 1 to 2047 > + */ -> + odr_sel_bits =3D DIV_ROUND_CLOSEST(fclk, odr * 32); +> + odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32); > + if (odr_sel_bits < 1) -> + odr_sel_bits =3D 1; +> + odr_sel_bits = 1; > + else if (odr_sel_bits > 2047) -> + odr_sel_bits =3D 2047; +> + odr_sel_bits = 2047; > + -> + ret =3D ad7124_spi_write_mask(st, AD7124_FILTER(channel), +> + ret = ad7124_spi_write_mask(st, AD7124_FILTER(channel), > + AD7124_FILTER_FS_MSK, > + AD7124_FILTER_FS(odr_sel_bits), 3); > + if (ret < 0) > + return ret; -> + /* fADC =3D fCLK / (FS[10:0] x 32) */ -> + st->channel_config[channel].odr =3D +> + /* fADC = fCLK / (FS[10:0] x 32) */ +> + st->channel_config[channel].odr = > + DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32); > + > + return 0; @@ -374,17 +366,17 @@ annel) > + struct iio_chan_spec const *chan, > + int *val, int *val2, long info) > +{ -> + struct ad7124_state *st =3D iio_priv(indio_dev); +> + struct ad7124_state *st = iio_priv(indio_dev); > + int idx, ret; > + > + switch (info) { > + case IIO_CHAN_INFO_RAW: -> + ret =3D ad_sigma_delta_single_conversion(indio_dev, chan, val); +> + ret = ad_sigma_delta_single_conversion(indio_dev, chan, val); > + if (ret < 0) > + return ret; > + > + /* After the conversion is performed, disable the channel */ -> + ret =3D ad_sd_write_reg(&st->sd, +> + ret = ad_sd_write_reg(&st->sd, > + AD7124_CHANNEL(chan->address), 2, > + st->channel_config[chan->address].ain | > + AD7124_CHANNEL_EN(0)); @@ -393,28 +385,28 @@ annel) > + > + return IIO_VAL_INT; > + case IIO_CHAN_INFO_SCALE: -> + idx =3D st->channel_config[chan->address].pga_bits; -> + *val =3D st->channel_config[chan->address].vref_mv / +> + idx = st->channel_config[chan->address].pga_bits; +> + *val = st->channel_config[chan->address].vref_mv / > + ad7124_gain[idx]; > + if (st->channel_config[chan->address].bipolar) -> + *val2 =3D chan->scan_type.realbits - 1; +> + *val2 = chan->scan_type.realbits - 1; > + else -> + *val2 =3D chan->scan_type.realbits; +> + *val2 = chan->scan_type.realbits; > + > + return IIO_VAL_FRACTIONAL_LOG2; > + case IIO_CHAN_INFO_OFFSET: > + if (st->channel_config[chan->address].bipolar) { -> + /* Code =3D 2^(n =E2=88=92 1) =C3=97 ((Ain =C3=97 Gain / Vref) + 1) */ -> + idx =3D st->channel_config[chan->address].pga_bits; -> + *val =3D -(st->channel_config[chan->address].vref_mv / +> + /* Code = 2^(n − 1) × ((Ain × Gain / Vref) + 1) */ +> + idx = st->channel_config[chan->address].pga_bits; +> + *val = -(st->channel_config[chan->address].vref_mv / > + ad7124_gain[idx]); > + } else { -> + *val =3D 0; +> + *val = 0; > + } > + > + return IIO_VAL_INT; > + case IIO_CHAN_INFO_SAMP_FREQ: -> + *val =3D st->channel_config[chan->address].odr; +> + *val = st->channel_config[chan->address].odr; > + > + return IIO_VAL_INT; > + default: @@ -426,11 +418,11 @@ annel) > + struct iio_chan_spec const *chan, > + int val, int val2, long info) > +{ -> + struct ad7124_state *st =3D iio_priv(indio_dev); +> + struct ad7124_state *st = iio_priv(indio_dev); > + > + switch (info) { > + case IIO_CHAN_INFO_SAMP_FREQ: -> + if (val2 !=3D 0) +> + if (val2 != 0) > + return -EINVAL; > + > + return ad7124_set_channel_odr(st, chan->address, val); @@ -439,9 +431,9 @@ annel) > + } > +} > + -> +static const struct iio_info ad7124_info =3D { -> + .read_raw =3D ad7124_read_raw, -> + .write_raw =3D ad7124_write_raw, +> +static const struct iio_info ad7124_info = { +> + .read_raw = ad7124_read_raw, +> + .write_raw = ad7124_write_raw, > +}; > + > +static int ad7124_soft_reset(struct ad7124_state *st) @@ -449,13 +441,13 @@ annel) > + unsigned int readval, timeout; > + int ret; > + -> + ret =3D ad_sd_reset(&st->sd, 64); +> + ret = ad_sd_reset(&st->sd, 64); > + if (ret < 0) > + return ret; > + -> + timeout =3D 100; +> + timeout = 100; > + do { -> + ret =3D ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval); +> + ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval); > + if (ret < 0) > + return ret; > + @@ -474,7 +466,7 @@ annel) > +static int ad7124_init_channel_vref(struct ad7124_state *st, > + unsigned int channel_number) > +{ -> + unsigned int refsel =3D st->channel_config[channel_number].refsel; +> + unsigned int refsel = st->channel_config[channel_number].refsel; > + > + switch (refsel) { > + case AD7124_REFIN1: @@ -482,18 +474,17 @@ annel) > + case AD7124_AVDD_REF: > + if (IS_ERR(st->vref[refsel])) { > + dev_err(&st->sd.spi->dev, -> + "Error, trying to use external voltage reference without a %s regula= -tor.", +> + "Error, trying to use external voltage reference without a %s regulator.", > + ad7124_ref_names[refsel]); > + return PTR_ERR(st->vref[refsel]); > + } -> + st->channel_config[channel_number].vref_mv =3D +> + st->channel_config[channel_number].vref_mv = > + regulator_get_voltage(st->vref[refsel]); > + /* Conversion from uV to mV */ -> + st->channel_config[channel_number].vref_mv /=3D 1000; +> + st->channel_config[channel_number].vref_mv /= 1000; > + break; > + case AD7124_INT_REF: -> + st->channel_config[channel_number].vref_mv =3D 2500; +> + st->channel_config[channel_number].vref_mv = 2500; > + break; > + default: > + dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel); @@ -506,32 +497,32 @@ tor.", > +static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev, > + struct device_node *np) > +{ -> + struct ad7124_state *st =3D iio_priv(indio_dev); +> + struct ad7124_state *st = iio_priv(indio_dev); > + struct device_node *child; > + struct iio_chan_spec *chan; -> + unsigned int ain[2], channel =3D 0, tmp; +> + unsigned int ain[2], channel = 0, tmp; > + int ret, res; > + -> + st->num_channels =3D of_get_available_child_count(np); +> + st->num_channels = of_get_available_child_count(np); > + if (!st->num_channels) { > + dev_err(indio_dev->dev.parent, "no channel children\n"); > + return -ENODEV; > + } > + -> + chan =3D devm_kcalloc(indio_dev->dev.parent, st->num_channels, +> + chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels, > + sizeof(*chan), GFP_KERNEL); > + if (!chan) > + return -ENOMEM; > + -> + indio_dev->channels =3D chan; -> + indio_dev->num_channels =3D st->num_channels; +> + indio_dev->channels = chan; +> + indio_dev->num_channels = st->num_channels; > + > + for_each_available_child_of_node(np, child) { -> + ret =3D of_property_read_u32(child, "reg", &channel); +> + ret = of_property_read_u32(child, "reg", &channel); > + if (ret) > + goto err; > + -> + ret =3D of_property_read_u32_array(child, "adi,diff-channels", +> + ret = of_property_read_u32_array(child, "adi,diff-channels", > + ain, 2); This actually feels like something we could standardize as well as bipolar. @@ -543,31 +534,31 @@ is a reference select that has to be paired with channel choice. > + if (ret) > + goto err; > + -> + if (ain[0] >=3D st->chip_info->num_inputs || -> + ain[1] >=3D st->chip_info->num_inputs) { +> + if (ain[0] >= st->chip_info->num_inputs || +> + ain[1] >= st->chip_info->num_inputs) { > + dev_err(indio_dev->dev.parent, > + "Input pin number out of range.\n"); -> + ret =3D -EINVAL; +> + ret = -EINVAL; > + goto err; > + } -> + st->channel_config[channel].ain =3D AD7124_CHANNEL_AINP(ain[0]) | +> + st->channel_config[channel].ain = AD7124_CHANNEL_AINP(ain[0]) | > + AD7124_CHANNEL_AINM(ain[1]); -> + st->channel_config[channel].bipolar =3D +> + st->channel_config[channel].bipolar = > + of_property_read_bool(child, "adi,bipolar"); > + -> + ret =3D of_property_read_u32(child, "adi,reference-select", &tmp); +> + ret = of_property_read_u32(child, "adi,reference-select", &tmp); > + if (ret) -> + st->channel_config[channel].refsel =3D AD7124_INT_REF; +> + st->channel_config[channel].refsel = AD7124_INT_REF; > + else -> + st->channel_config[channel].refsel =3D tmp; +> + st->channel_config[channel].refsel = tmp; > + -> + ret =3D of_property_read_u32(child, "adi,gain", &tmp); +> + ret = of_property_read_u32(child, "adi,gain", &tmp); > + if (ret) { -> + st->channel_config[channel].pga_bits =3D 0; +> + st->channel_config[channel].pga_bits = 0; > + } else { -> + res =3D ad7124_find_closest_match(ad7124_gain, +> + res = ad7124_find_closest_match(ad7124_gain, > + ARRAY_SIZE(ad7124_gain), tmp); -> + st->channel_config[channel].pga_bits =3D res; +> + st->channel_config[channel].pga_bits = res; Hmm. The old question of what to put in DT as it reflects wiring and what to leave to userspace. Gain is tricky as only some values make sense for a given system, but there can be more than one that does... @@ -577,7 +568,7 @@ it later if it wanted to. > + } > + -> + ret =3D of_property_read_u32(child, "adi,odr-hz", &tmp); +> + ret = of_property_read_u32(child, "adi,odr-hz", &tmp); Why is this in DT. This one feels like a userspace choice to me. It's only tangentially connected to how things are connected on the board. @@ -590,15 +581,15 @@ anyway. > + * 9 SPS is the minimum output data rate supported > + * regardless of the selected power mode. > + */ -> + st->channel_config[channel].odr =3D 9; +> + st->channel_config[channel].odr = 9; > + else -> + st->channel_config[channel].odr =3D tmp; +> + st->channel_config[channel].odr = tmp; > + -> + *chan =3D ad7124_channel_template; -> + chan->address =3D channel; -> + chan->scan_index =3D channel; -> + chan->channel =3D ain[0]; -> + chan->channel2 =3D ain[1]; +> + *chan = ad7124_channel_template; +> + chan->address = channel; +> + chan->scan_index = channel; +> + chan->channel = ain[0]; +> + chan->channel2 = ain[1]; > + > + chan++; > + } @@ -615,46 +606,45 @@ anyway. > + unsigned int val, fclk, power_mode; > + int i, ret; > + -> + fclk =3D clk_get_rate(st->mclk); +> + fclk = clk_get_rate(st->mclk); > + if (!fclk) > + return -EINVAL; > + > + /* The power mode changes the master clock frequency */ -> + power_mode =3D ad7124_find_closest_match(ad7124_master_clk_freq_hz, +> + power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz, > + ARRAY_SIZE(ad7124_master_clk_freq_hz), > + fclk); -> + if (fclk !=3D ad7124_master_clk_freq_hz[power_mode]) { -> + ret =3D clk_set_rate(st->mclk, fclk); +> + if (fclk != ad7124_master_clk_freq_hz[power_mode]) { +> + ret = clk_set_rate(st->mclk, fclk); > + if (ret) > + return ret; > + } > + > + /* Set the power mode */ -> + st->adc_control &=3D ~AD7124_ADC_CTRL_PWR_MSK; -> + st->adc_control |=3D AD7124_ADC_CTRL_PWR(power_mode); -> + ret =3D ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control= -); +> + st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK; +> + st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode); +> + ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control); > + if (ret < 0) > + return ret; > + -> + for (i =3D 0; i < st->num_channels; i++) { -> + val =3D st->channel_config[i].ain | AD7124_CHANNEL_SETUP(i); -> + ret =3D ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, val); +> + for (i = 0; i < st->num_channels; i++) { +> + val = st->channel_config[i].ain | AD7124_CHANNEL_SETUP(i); +> + ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, val); > + if (ret < 0) > + return ret; > + -> + ret =3D ad7124_init_channel_vref(st, i); +> + ret = ad7124_init_channel_vref(st, i); > + if (ret < 0) > + return ret; > + -> + val =3D AD7124_CONFIG_BIPOLAR(st->channel_config[i].bipolar) | +> + val = AD7124_CONFIG_BIPOLAR(st->channel_config[i].bipolar) | > + AD7124_CONFIG_REF_SEL(st->channel_config[i].refsel) | > + AD7124_CONFIG_PGA(st->channel_config[i].pga_bits); -> + ret =3D ad_sd_write_reg(&st->sd, AD7124_CONFIG(i), 2, val); +> + ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(i), 2, val); > + if (ret < 0) > + return ret; > + -> + ret =3D ad7124_set_channel_odr(st, i, st->channel_config[i].odr); +> + ret = ad7124_set_channel_odr(st, i, st->channel_config[i].odr); > + if (ret < 0) > + return ret; > + } @@ -669,66 +659,66 @@ anyway. > + struct iio_dev *indio_dev; > + int i, ret; > + -> + indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*st)); +> + indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); > + if (!indio_dev) > + return -ENOMEM; > + -> + st =3D iio_priv(indio_dev); +> + st = iio_priv(indio_dev); > + -> + id =3D spi_get_device_id(spi); -> + st->chip_info =3D &ad7124_chip_info_tbl[id->driver_data]; +> + id = spi_get_device_id(spi); +> + st->chip_info = &ad7124_chip_info_tbl[id->driver_data]; > + > + ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info); > + > + spi_set_drvdata(spi, indio_dev); > + -> + indio_dev->dev.parent =3D &spi->dev; -> + indio_dev->name =3D spi_get_device_id(spi)->name; -> + indio_dev->modes =3D INDIO_DIRECT_MODE; -> + indio_dev->info =3D &ad7124_info; +> + indio_dev->dev.parent = &spi->dev; +> + indio_dev->name = spi_get_device_id(spi)->name; +> + indio_dev->modes = INDIO_DIRECT_MODE; +> + indio_dev->info = &ad7124_info; > + -> + ret =3D ad7124_of_parse_channel_config(indio_dev, spi->dev.of_node); +> + ret = ad7124_of_parse_channel_config(indio_dev, spi->dev.of_node); > + if (ret < 0) > + return ret; > + -> + for (i =3D 0; i < ARRAY_SIZE(st->vref); i++) { -> + if (i !=3D AD7124_INT_REF) { -> + st->vref[i] =3D devm_regulator_get_optional(&spi->dev, +> + for (i = 0; i < ARRAY_SIZE(st->vref); i++) { +> + if (i != AD7124_INT_REF) { +> + st->vref[i] = devm_regulator_get_optional(&spi->dev, > + ad7124_ref_names[i]); -> + if (PTR_ERR(st->vref[i]) =3D=3D -ENODEV) +> + if (PTR_ERR(st->vref[i]) == -ENODEV) > + continue; > + else if (IS_ERR(st->vref[i])) > + return PTR_ERR(st->vref[i]); > + -> + ret =3D regulator_enable(st->vref[i]); +> + ret = regulator_enable(st->vref[i]); > + if (ret) > + return ret; > + } > + } > + -> + st->mclk =3D devm_clk_get(&spi->dev, "mclk"); +> + st->mclk = devm_clk_get(&spi->dev, "mclk"); > + if (IS_ERR(st->mclk)) { -> + ret =3D PTR_ERR(st->mclk); +> + ret = PTR_ERR(st->mclk); > + goto error_regulator_disable; > + } > + -> + ret =3D clk_prepare_enable(st->mclk); +> + ret = clk_prepare_enable(st->mclk); > + if (ret < 0) > + goto error_regulator_disable; > + -> + ret =3D ad7124_soft_reset(st); +> + ret = ad7124_soft_reset(st); > + if (ret < 0) > + goto error_clk_disable_unprepare; > + -> + ret =3D ad7124_setup(st); +> + ret = ad7124_setup(st); > + if (ret < 0) > + goto error_clk_disable_unprepare; > + -> + ret =3D ad_sd_setup_buffer_and_trigger(indio_dev); +> + ret = ad_sd_setup_buffer_and_trigger(indio_dev); > + if (ret < 0) > + goto error_clk_disable_unprepare; > + -> + ret =3D iio_device_register(indio_dev); +> + ret = iio_device_register(indio_dev); > + if (ret < 0) { > + dev_err(&spi->dev, "Failed to register iio device\n"); > + goto error_remove_trigger; @@ -741,7 +731,7 @@ anyway. > +error_clk_disable_unprepare: > + clk_disable_unprepare(st->mclk); > +error_regulator_disable: -> + for (i =3D ARRAY_SIZE(st->vref) - 1; i >=3D 0; i--) { +> + for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) { > + if (!IS_ERR_OR_NULL(st->vref[i])) > + regulator_disable(st->vref[i]); > + } @@ -751,8 +741,8 @@ anyway. > + > +static int ad7124_remove(struct spi_device *spi) > +{ -> + struct iio_dev *indio_dev =3D spi_get_drvdata(spi); -> + struct ad7124_state *st =3D iio_priv(indio_dev); +> + struct iio_dev *indio_dev = spi_get_drvdata(spi); +> + struct ad7124_state *st = iio_priv(indio_dev); > + int i; > + > + iio_device_unregister(indio_dev); @@ -766,7 +756,7 @@ I like to be able to check the ordering only once rather than twice when reviewing so will always confirm they match. > + -> + for (i =3D ARRAY_SIZE(st->vref) - 1; i >=3D 0; i--) { +> + for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) { > + if (!IS_ERR_OR_NULL(st->vref[i])) > + regulator_disable(st->vref[i]); > + } @@ -774,28 +764,28 @@ when reviewing so will always confirm they match. > + return 0; > +} > + -> +static const struct spi_device_id ad7124_id_table[] =3D { +> +static const struct spi_device_id ad7124_id_table[] = { > + { "ad7124-4", ID_AD7124_4 }, > + { "ad7124-8", ID_AD7124_8 }, > + {} > +}; > +MODULE_DEVICE_TABLE(spi, ad7124_id_table); > + -> +static const struct of_device_id ad7124_of_match[] =3D { -> + { .compatible =3D "adi,ad7124-4" }, -> + { .compatible =3D "adi,ad7124-8" }, +> +static const struct of_device_id ad7124_of_match[] = { +> + { .compatible = "adi,ad7124-4" }, +> + { .compatible = "adi,ad7124-8" }, > + { }, > +}; > +MODULE_DEVICE_TABLE(of, ad7124_of_match); > + -> +static struct spi_driver ad71124_driver =3D { -> + .driver =3D { -> + .name =3D "ad7124", -> + .of_match_table =3D ad7124_of_match, +> +static struct spi_driver ad71124_driver = { +> + .driver = { +> + .name = "ad7124", +> + .of_match_table = ad7124_of_match, > + }, -> + .probe =3D ad7124_probe, -> + .remove =3D ad7124_remove, -> + .id_table =3D ad7124_id_table, +> + .probe = ad7124_probe, +> + .remove = ad7124_remove, +> + .id_table = ad7124_id_table, > +}; > +module_spi_driver(ad71124_driver); > + diff --git a/a/content_digest b/N1/content_digest index 37e8676..7f5b32f 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -17,23 +17,21 @@ "\n" "> The ad7124-4 and ad7124-8 are a family of 4 and 8 channel sigma-delta ADCs\n" "> with 24-bit precision and reference.\n" - ">=20\n" + "> \n" "> Three power modes are available which in turn affect the output data rate:\n" "> * Full power: 9.38 SPS to 19,200 SPS\n" "> * Mid power: 2.34 SPS to 4800 SPS\n" "> * Low power: 1.17 SPS to 2400 SPS\n" - ">=20\n" + "> \n" "> The ad7124-4 can be configured to have four differential inputs, while\n" "> ad7124-8 can have 8. Moreover, ad7124 also supports per channel\n" "> configuration. Each configuration consists of gain, reference source,\n" "> output data rate and bipolar/unipolar configuration.\n" - ">=20\n" + "> \n" "> Datasheets:\n" - "> Link: http://www.analog.com/media/en/technical-documentation/data-sheets/=\n" - "AD7124-4.pdf\n" - "> Link: http://www.analog.com/media/en/technical-documentation/data-sheets/=\n" - "ad7124-8.pdf\n" - ">=20\n" + "> Link: http://www.analog.com/media/en/technical-documentation/data-sheets/AD7124-4.pdf\n" + "> Link: http://www.analog.com/media/en/technical-documentation/data-sheets/ad7124-8.pdf\n" + "> \n" "> Signed-off-by: Stefan Popa <stefan.popa@analog.com>\n" "Hi Stefan,\n" "\n" @@ -60,25 +58,20 @@ "> \t- Removed channel, address, scan_index and shift fields from\n" "> \t ad7124_channel_template.\n" "> \t- Added a sanity check for val2 in ad7124_write_raw().\n" - "> \t- Used the \"reg\" property to get the channel address and \"adi,diff-chann=\n" - "els\"\n" - "> \t for the differential pins. The \"adi,channel-number\" property was remov=\n" - "ed.\n" - "> \t- When calling regulator_get_optional, the probe is given up in case of =\n" - "error,\n" + "> \t- Used the \"reg\" property to get the channel address and \"adi,diff-channels\"\n" + "> \t for the differential pins. The \"adi,channel-number\" property was removed.\n" + "> \t- When calling regulator_get_optional, the probe is given up in case of error,\n" "> \t but continues in case of -ENODEV.\n" - "> \t- clk_disable_unprepare() is called before ad_sd_cleanup_buffer_and_trig=\n" - "ger\n" + "> \t- clk_disable_unprepare() is called before ad_sd_cleanup_buffer_and_trigger\n" "> \t in ad7124_remove().\n" - ">=20\n" + "> \n" "> MAINTAINERS | 7 +\n" "> drivers/iio/adc/Kconfig | 11 +\n" "> drivers/iio/adc/Makefile | 1 +\n" - "> drivers/iio/adc/ad7124.c | 648 +++++++++++++++++++++++++++++++++++++++++=\n" - "++++++\n" + "> drivers/iio/adc/ad7124.c | 648 +++++++++++++++++++++++++++++++++++++++++++++++\n" "> 4 files changed, 667 insertions(+)\n" "> create mode 100644 drivers/iio/adc/ad7124.c\n" - ">=20\n" + "> \n" "> diff --git a/MAINTAINERS b/MAINTAINERS\n" "> index f642044..3a1bfcb 100644\n" "> --- a/MAINTAINERS\n" @@ -86,7 +79,7 @@ "> @@ -839,6 +839,13 @@ S:\tSupported\n" "> F:\tdrivers/iio/dac/ad5758.c\n" "> F:\tDocumentation/devicetree/bindings/iio/dac/ad5758.txt\n" - "> =20\n" + "> \n" "> +ANALOG DEVICES INC AD7124 DRIVER\n" "> +M:\tStefan Popa <stefan.popa@analog.com>\n" "> +L:\tlinux-iio@vger.kernel.org\n" @@ -104,7 +97,7 @@ "> @@ -10,6 +10,17 @@ config AD_SIGMA_DELTA\n" "> \tselect IIO_BUFFER\n" "> \tselect IIO_TRIGGERED_BUFFER\n" - "> =20\n" + "> \n" "> +config AD7124\n" "> +\ttristate \"Analog Devices AD7124 and similar sigma-delta ADCs driver\"\n" "> +\tdepends on SPI_MASTER\n" @@ -124,13 +117,13 @@ "> --- a/drivers/iio/adc/Makefile\n" "> +++ b/drivers/iio/adc/Makefile\n" "> @@ -5,6 +5,7 @@\n" - "> =20\n" + "> \n" "> # When adding new entries keep the list in alphabetical order\n" - "> obj-$(CONFIG_AD_SIGMA_DELTA) +=3D ad_sigma_delta.o\n" - "> +obj-$(CONFIG_AD7124) +=3D ad7124.o\n" - "> obj-$(CONFIG_AD7266) +=3D ad7266.o\n" - "> obj-$(CONFIG_AD7291) +=3D ad7291.o\n" - "> obj-$(CONFIG_AD7298) +=3D ad7298.o\n" + "> obj-$(CONFIG_AD_SIGMA_DELTA) += ad_sigma_delta.o\n" + "> +obj-$(CONFIG_AD7124) += ad7124.o\n" + "> obj-$(CONFIG_AD7266) += ad7266.o\n" + "> obj-$(CONFIG_AD7291) += ad7291.o\n" + "> obj-$(CONFIG_AD7298) += ad7298.o\n" "> diff --git a/drivers/iio/adc/ad7124.c b/drivers/iio/adc/ad7124.c\n" "> new file mode 100644\n" "> index 0000000..0660135\n" @@ -223,21 +216,21 @@ "> +\tAD7124_FULL_POWER,\n" "> +};\n" "> +\n" - "> +static const unsigned int ad7124_gain[8] =3D {\n" + "> +static const unsigned int ad7124_gain[8] = {\n" "> +\t1, 2, 4, 8, 16, 32, 64, 128\n" "> +};\n" "> +\n" - "> +static const int ad7124_master_clk_freq_hz[3] =3D {\n" - "> +\t[AD7124_LOW_POWER] =3D 76800,\n" - "> +\t[AD7124_MID_POWER] =3D 153600,\n" - "> +\t[AD7124_FULL_POWER] =3D 614400,\n" + "> +static const int ad7124_master_clk_freq_hz[3] = {\n" + "> +\t[AD7124_LOW_POWER] = 76800,\n" + "> +\t[AD7124_MID_POWER] = 153600,\n" + "> +\t[AD7124_FULL_POWER] = 614400,\n" "> +};\n" "> +\n" - "> +static const char * const ad7124_ref_names[] =3D {\n" - "> +\t[AD7124_REFIN1] =3D \"refin1\",\n" - "> +\t[AD7124_REFIN2] =3D \"refin2\",\n" - "> +\t[AD7124_INT_REF] =3D \"int\",\n" - "> +\t[AD7124_AVDD_REF] =3D \"avdd\",\n" + "> +static const char * const ad7124_ref_names[] = {\n" + "> +\t[AD7124_REFIN1] = \"refin1\",\n" + "> +\t[AD7124_REFIN2] = \"refin2\",\n" + "> +\t[AD7124_INT_REF] = \"int\",\n" + "> +\t[AD7124_AVDD_REF] = \"avdd\",\n" "> +};\n" "> +\n" "> +struct ad7124_chip_info {\n" @@ -263,27 +256,27 @@ "> +\tunsigned int num_channels;\n" "> +};\n" "> +\n" - "> +static const struct iio_chan_spec ad7124_channel_template =3D {\n" - "> +\t.type =3D IIO_VOLTAGE,\n" - "> +\t.indexed =3D 1,\n" - "> +\t.differential =3D 1,\n" - "> +\t.info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) |\n" + "> +static const struct iio_chan_spec ad7124_channel_template = {\n" + "> +\t.type = IIO_VOLTAGE,\n" + "> +\t.indexed = 1,\n" + "> +\t.differential = 1,\n" + "> +\t.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |\n" "> +\t\tBIT(IIO_CHAN_INFO_SCALE) |\n" "> +\t\tBIT(IIO_CHAN_INFO_OFFSET) |\n" "> +\t\tBIT(IIO_CHAN_INFO_SAMP_FREQ),\n" - "> +\t.scan_type =3D {\n" - "> +\t\t.sign =3D 'u',\n" - "> +\t\t.realbits =3D 24,\n" - "> +\t\t.storagebits =3D 32,\n" + "> +\t.scan_type = {\n" + "> +\t\t.sign = 'u',\n" + "> +\t\t.realbits = 24,\n" + "> +\t\t.storagebits = 32,\n" "> +\t},\n" "> +};\n" "> +\n" - "> +static struct ad7124_chip_info ad7124_chip_info_tbl[] =3D {\n" - "> +\t[ID_AD7124_4] =3D {\n" - "> +\t\t.num_inputs =3D 8,\n" + "> +static struct ad7124_chip_info ad7124_chip_info_tbl[] = {\n" + "> +\t[ID_AD7124_4] = {\n" + "> +\t\t.num_inputs = 8,\n" "> +\t},\n" - "> +\t[ID_AD7124_8] =3D {\n" - "> +\t\t.num_inputs =3D 16,\n" + "> +\t[ID_AD7124_8] = {\n" + "> +\t\t.num_inputs = 16,\n" "> +\t},\n" "> +};\n" "> +\n" @@ -292,8 +285,8 @@ "> +{\n" "> +\tint i;\n" "> +\n" - "> +\tfor (i =3D 0; i < size; i++) {\n" - "> +\t\tif (val <=3D array[i])\n" + "> +\tfor (i = 0; i < size; i++) {\n" + "> +\t\tif (val <= array[i])\n" "> +\t\t\treturn i;\n" "> +\t}\n" "> +\n" @@ -309,12 +302,12 @@ "> +\tunsigned int readval;\n" "> +\tint ret;\n" "> +\n" - "> +\tret =3D ad_sd_read_reg(&st->sd, addr, bytes, &readval);\n" + "> +\tret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);\n" "> +\tif (ret < 0)\n" "> +\t\treturn ret;\n" "> +\n" - "> +\treadval &=3D ~mask;\n" - "> +\treadval |=3D val;\n" + "> +\treadval &= ~mask;\n" + "> +\treadval |= val;\n" "> +\n" "> +\treturn ad_sd_write_reg(&st->sd, addr, bytes, readval);\n" "> +}\n" @@ -322,33 +315,32 @@ "> +static int ad7124_set_mode(struct ad_sigma_delta *sd,\n" "> +\t\t\t enum ad_sigma_delta_mode mode)\n" "> +{\n" - "> +\tstruct ad7124_state *st =3D container_of(sd, struct ad7124_state, sd);\n" + "> +\tstruct ad7124_state *st = container_of(sd, struct ad7124_state, sd);\n" "> +\n" - "> +\tst->adc_control &=3D ~AD7124_ADC_CTRL_MODE_MSK;\n" - "> +\tst->adc_control |=3D AD7124_ADC_CTRL_MODE(mode);\n" + "> +\tst->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;\n" + "> +\tst->adc_control |= AD7124_ADC_CTRL_MODE(mode);\n" "> +\n" "> +\treturn ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);\n" "> +}\n" "> +\n" - "> +static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int ch=\n" - "annel)\n" + "> +static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)\n" "> +{\n" - "> +\tstruct ad7124_state *st =3D container_of(sd, struct ad7124_state, sd);\n" + "> +\tstruct ad7124_state *st = container_of(sd, struct ad7124_state, sd);\n" "> +\tunsigned int val;\n" "> +\n" - "> +\tval =3D st->channel_config[channel].ain | AD7124_CHANNEL_EN(1) |\n" + "> +\tval = st->channel_config[channel].ain | AD7124_CHANNEL_EN(1) |\n" "> +\t AD7124_CHANNEL_SETUP(channel);\n" "> +\n" "> +\treturn ad_sd_write_reg(&st->sd, AD7124_CHANNEL(channel), 2, val);\n" "> +}\n" "> +\n" - "> +static const struct ad_sigma_delta_info ad7124_sigma_delta_info =3D {\n" - "> +\t.set_channel =3D ad7124_set_channel,\n" - "> +\t.set_mode =3D ad7124_set_mode,\n" - "> +\t.has_registers =3D true,\n" - "> +\t.addr_shift =3D 0,\n" - "> +\t.read_mask =3D BIT(6),\n" - "> +\t.data_reg =3D AD7124_DATA,\n" + "> +static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {\n" + "> +\t.set_channel = ad7124_set_channel,\n" + "> +\t.set_mode = ad7124_set_mode,\n" + "> +\t.has_registers = true,\n" + "> +\t.addr_shift = 0,\n" + "> +\t.read_mask = BIT(6),\n" + "> +\t.data_reg = AD7124_DATA,\n" "> +};\n" "> +\n" "> +static int ad7124_set_channel_odr(struct ad7124_state *st,\n" @@ -358,27 +350,27 @@ "> +\tunsigned int fclk, odr_sel_bits;\n" "> +\tint ret;\n" "> +\n" - "> +\tfclk =3D clk_get_rate(st->mclk);\n" + "> +\tfclk = clk_get_rate(st->mclk);\n" "> +\t/*\n" - "> +\t * FS[10:0] =3D fCLK / (fADC x 32) where:\n" + "> +\t * FS[10:0] = fCLK / (fADC x 32) where:\n" "> +\t * fADC is the output data rate\n" "> +\t * fCLK is the master clock frequency\n" "> +\t * FS[10:0] are the bits in the filter register\n" "> +\t * FS[10:0] can have a value from 1 to 2047\n" "> +\t */\n" - "> +\todr_sel_bits =3D DIV_ROUND_CLOSEST(fclk, odr * 32);\n" + "> +\todr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);\n" "> +\tif (odr_sel_bits < 1)\n" - "> +\t\todr_sel_bits =3D 1;\n" + "> +\t\todr_sel_bits = 1;\n" "> +\telse if (odr_sel_bits > 2047)\n" - "> +\t\todr_sel_bits =3D 2047;\n" + "> +\t\todr_sel_bits = 2047;\n" "> +\n" - "> +\tret =3D ad7124_spi_write_mask(st, AD7124_FILTER(channel),\n" + "> +\tret = ad7124_spi_write_mask(st, AD7124_FILTER(channel),\n" "> +\t\t\t\t AD7124_FILTER_FS_MSK,\n" "> +\t\t\t\t AD7124_FILTER_FS(odr_sel_bits), 3);\n" "> +\tif (ret < 0)\n" "> +\t\treturn ret;\n" - "> +\t/* fADC =3D fCLK / (FS[10:0] x 32) */\n" - "> +\tst->channel_config[channel].odr =3D\n" + "> +\t/* fADC = fCLK / (FS[10:0] x 32) */\n" + "> +\tst->channel_config[channel].odr =\n" "> +\t\tDIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);\n" "> +\n" "> +\treturn 0;\n" @@ -388,17 +380,17 @@ "> +\t\t\t struct iio_chan_spec const *chan,\n" "> +\t\t\t int *val, int *val2, long info)\n" "> +{\n" - "> +\tstruct ad7124_state *st =3D iio_priv(indio_dev);\n" + "> +\tstruct ad7124_state *st = iio_priv(indio_dev);\n" "> +\tint idx, ret;\n" "> +\n" "> +\tswitch (info) {\n" "> +\tcase IIO_CHAN_INFO_RAW:\n" - "> +\t\tret =3D ad_sigma_delta_single_conversion(indio_dev, chan, val);\n" + "> +\t\tret = ad_sigma_delta_single_conversion(indio_dev, chan, val);\n" "> +\t\tif (ret < 0)\n" "> +\t\t\treturn ret;\n" "> +\n" "> +\t\t/* After the conversion is performed, disable the channel */\n" - "> +\t\tret =3D ad_sd_write_reg(&st->sd,\n" + "> +\t\tret = ad_sd_write_reg(&st->sd,\n" "> +\t\t\t\t AD7124_CHANNEL(chan->address), 2,\n" "> +\t\t\t\t st->channel_config[chan->address].ain |\n" "> +\t\t\t\t AD7124_CHANNEL_EN(0));\n" @@ -407,28 +399,28 @@ "> +\n" "> +\t\treturn IIO_VAL_INT;\n" "> +\tcase IIO_CHAN_INFO_SCALE:\n" - "> +\t\tidx =3D st->channel_config[chan->address].pga_bits;\n" - "> +\t\t*val =3D st->channel_config[chan->address].vref_mv /\n" + "> +\t\tidx = st->channel_config[chan->address].pga_bits;\n" + "> +\t\t*val = st->channel_config[chan->address].vref_mv /\n" "> +\t\t\tad7124_gain[idx];\n" "> +\t\tif (st->channel_config[chan->address].bipolar)\n" - "> +\t\t\t*val2 =3D chan->scan_type.realbits - 1;\n" + "> +\t\t\t*val2 = chan->scan_type.realbits - 1;\n" "> +\t\telse\n" - "> +\t\t\t*val2 =3D chan->scan_type.realbits;\n" + "> +\t\t\t*val2 = chan->scan_type.realbits;\n" "> +\n" "> +\t\treturn IIO_VAL_FRACTIONAL_LOG2;\n" "> +\tcase IIO_CHAN_INFO_OFFSET:\n" "> +\t\tif (st->channel_config[chan->address].bipolar) {\n" - "> +\t\t\t/* Code =3D 2^(n =E2=88=92 1) =C3=97 ((Ain =C3=97 Gain / Vref) + 1) */\n" - "> +\t\t\tidx =3D st->channel_config[chan->address].pga_bits;\n" - "> +\t\t\t*val =3D -(st->channel_config[chan->address].vref_mv /\n" + "> +\t\t\t/* Code = 2^(n \342\210\222 1) \303\227 ((Ain \303\227 Gain / Vref) + 1) */\n" + "> +\t\t\tidx = st->channel_config[chan->address].pga_bits;\n" + "> +\t\t\t*val = -(st->channel_config[chan->address].vref_mv /\n" "> +\t\t\t\t ad7124_gain[idx]);\n" "> +\t\t} else {\n" - "> +\t\t\t*val =3D 0;\n" + "> +\t\t\t*val = 0;\n" "> +\t\t}\n" "> +\n" "> +\t\treturn IIO_VAL_INT;\n" "> +\tcase IIO_CHAN_INFO_SAMP_FREQ:\n" - "> +\t\t*val =3D st->channel_config[chan->address].odr;\n" + "> +\t\t*val = st->channel_config[chan->address].odr;\n" "> +\n" "> +\t\treturn IIO_VAL_INT;\n" "> +\tdefault:\n" @@ -440,11 +432,11 @@ "> +\t\t\t struct iio_chan_spec const *chan,\n" "> +\t\t\t int val, int val2, long info)\n" "> +{\n" - "> +\tstruct ad7124_state *st =3D iio_priv(indio_dev);\n" + "> +\tstruct ad7124_state *st = iio_priv(indio_dev);\n" "> +\n" "> +\tswitch (info) {\n" "> +\tcase IIO_CHAN_INFO_SAMP_FREQ:\n" - "> +\t\tif (val2 !=3D 0)\n" + "> +\t\tif (val2 != 0)\n" "> +\t\t\treturn -EINVAL;\n" "> +\n" "> +\t\treturn ad7124_set_channel_odr(st, chan->address, val);\n" @@ -453,9 +445,9 @@ "> +\t}\n" "> +}\n" "> +\n" - "> +static const struct iio_info ad7124_info =3D {\n" - "> +\t.read_raw =3D ad7124_read_raw,\n" - "> +\t.write_raw =3D ad7124_write_raw,\n" + "> +static const struct iio_info ad7124_info = {\n" + "> +\t.read_raw = ad7124_read_raw,\n" + "> +\t.write_raw = ad7124_write_raw,\n" "> +};\n" "> +\n" "> +static int ad7124_soft_reset(struct ad7124_state *st)\n" @@ -463,13 +455,13 @@ "> +\tunsigned int readval, timeout;\n" "> +\tint ret;\n" "> +\n" - "> +\tret =3D ad_sd_reset(&st->sd, 64);\n" + "> +\tret = ad_sd_reset(&st->sd, 64);\n" "> +\tif (ret < 0)\n" "> +\t\treturn ret;\n" "> +\n" - "> +\ttimeout =3D 100;\n" + "> +\ttimeout = 100;\n" "> +\tdo {\n" - "> +\t\tret =3D ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);\n" + "> +\t\tret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);\n" "> +\t\tif (ret < 0)\n" "> +\t\t\treturn ret;\n" "> +\n" @@ -488,7 +480,7 @@ "> +static int ad7124_init_channel_vref(struct ad7124_state *st,\n" "> +\t\t\t\t unsigned int channel_number)\n" "> +{\n" - "> +\tunsigned int refsel =3D st->channel_config[channel_number].refsel;\n" + "> +\tunsigned int refsel = st->channel_config[channel_number].refsel;\n" "> +\n" "> +\tswitch (refsel) {\n" "> +\tcase AD7124_REFIN1:\n" @@ -496,18 +488,17 @@ "> +\tcase AD7124_AVDD_REF:\n" "> +\t\tif (IS_ERR(st->vref[refsel])) {\n" "> +\t\t\tdev_err(&st->sd.spi->dev,\n" - "> +\t\t\t\t\"Error, trying to use external voltage reference without a %s regula=\n" - "tor.\",\n" + "> +\t\t\t\t\"Error, trying to use external voltage reference without a %s regulator.\",\n" "> +\t\t\t\tad7124_ref_names[refsel]);\n" "> +\t\t\t\treturn PTR_ERR(st->vref[refsel]);\n" "> +\t\t}\n" - "> +\t\tst->channel_config[channel_number].vref_mv =3D\n" + "> +\t\tst->channel_config[channel_number].vref_mv =\n" "> +\t\t\tregulator_get_voltage(st->vref[refsel]);\n" "> +\t\t/* Conversion from uV to mV */\n" - "> +\t\tst->channel_config[channel_number].vref_mv /=3D 1000;\n" + "> +\t\tst->channel_config[channel_number].vref_mv /= 1000;\n" "> +\t\tbreak;\n" "> +\tcase AD7124_INT_REF:\n" - "> +\t\tst->channel_config[channel_number].vref_mv =3D 2500;\n" + "> +\t\tst->channel_config[channel_number].vref_mv = 2500;\n" "> +\t\tbreak;\n" "> +\tdefault:\n" "> +\t\tdev_err(&st->sd.spi->dev, \"Invalid reference %d\\n\", refsel);\n" @@ -520,32 +511,32 @@ "> +static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev,\n" "> +\t\t\t\t\t struct device_node *np)\n" "> +{\n" - "> +\tstruct ad7124_state *st =3D iio_priv(indio_dev);\n" + "> +\tstruct ad7124_state *st = iio_priv(indio_dev);\n" "> +\tstruct device_node *child;\n" "> +\tstruct iio_chan_spec *chan;\n" - "> +\tunsigned int ain[2], channel =3D 0, tmp;\n" + "> +\tunsigned int ain[2], channel = 0, tmp;\n" "> +\tint ret, res;\n" "> +\n" - "> +\tst->num_channels =3D of_get_available_child_count(np);\n" + "> +\tst->num_channels = of_get_available_child_count(np);\n" "> +\tif (!st->num_channels) {\n" "> +\t\tdev_err(indio_dev->dev.parent, \"no channel children\\n\");\n" "> +\t\treturn -ENODEV;\n" "> +\t}\n" "> +\n" - "> +\tchan =3D devm_kcalloc(indio_dev->dev.parent, st->num_channels,\n" + "> +\tchan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,\n" "> +\t\t\t sizeof(*chan), GFP_KERNEL);\n" "> +\tif (!chan)\n" "> +\t\treturn -ENOMEM;\n" "> +\n" - "> +\tindio_dev->channels =3D chan;\n" - "> +\tindio_dev->num_channels =3D st->num_channels;\n" + "> +\tindio_dev->channels = chan;\n" + "> +\tindio_dev->num_channels = st->num_channels;\n" "> +\n" "> +\tfor_each_available_child_of_node(np, child) {\n" - "> +\t\tret =3D of_property_read_u32(child, \"reg\", &channel);\n" + "> +\t\tret = of_property_read_u32(child, \"reg\", &channel);\n" "> +\t\tif (ret)\n" "> +\t\t\tgoto err;\n" "> +\n" - "> +\t\tret =3D of_property_read_u32_array(child, \"adi,diff-channels\",\n" + "> +\t\tret = of_property_read_u32_array(child, \"adi,diff-channels\",\n" "> +\t\t\t\t\t\t ain, 2);\n" "\n" "This actually feels like something we could standardize as well as bipolar.\n" @@ -557,31 +548,31 @@ "> +\t\tif (ret)\n" "> +\t\t\tgoto err;\n" "> +\n" - "> +\t\tif (ain[0] >=3D st->chip_info->num_inputs ||\n" - "> +\t\t ain[1] >=3D st->chip_info->num_inputs) {\n" + "> +\t\tif (ain[0] >= st->chip_info->num_inputs ||\n" + "> +\t\t ain[1] >= st->chip_info->num_inputs) {\n" "> +\t\t\tdev_err(indio_dev->dev.parent,\n" "> +\t\t\t\t\"Input pin number out of range.\\n\");\n" - "> +\t\t\tret =3D -EINVAL;\n" + "> +\t\t\tret = -EINVAL;\n" "> +\t\t\tgoto err;\n" "> +\t\t}\n" - "> +\t\tst->channel_config[channel].ain =3D AD7124_CHANNEL_AINP(ain[0]) |\n" + "> +\t\tst->channel_config[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |\n" "> +\t\t\t\t\t\t AD7124_CHANNEL_AINM(ain[1]);\n" - "> +\t\tst->channel_config[channel].bipolar =3D\n" + "> +\t\tst->channel_config[channel].bipolar =\n" "> +\t\t\tof_property_read_bool(child, \"adi,bipolar\");\n" "> +\n" - "> +\t\tret =3D of_property_read_u32(child, \"adi,reference-select\", &tmp);\n" + "> +\t\tret = of_property_read_u32(child, \"adi,reference-select\", &tmp);\n" "> +\t\tif (ret)\n" - "> +\t\t\tst->channel_config[channel].refsel =3D AD7124_INT_REF;\n" + "> +\t\t\tst->channel_config[channel].refsel = AD7124_INT_REF;\n" "> +\t\telse\n" - "> +\t\t\tst->channel_config[channel].refsel =3D tmp;\n" + "> +\t\t\tst->channel_config[channel].refsel = tmp;\n" "> +\n" - "> +\t\tret =3D of_property_read_u32(child, \"adi,gain\", &tmp);\n" + "> +\t\tret = of_property_read_u32(child, \"adi,gain\", &tmp);\n" "> +\t\tif (ret) {\n" - "> +\t\t\tst->channel_config[channel].pga_bits =3D 0;\n" + "> +\t\t\tst->channel_config[channel].pga_bits = 0;\n" "> +\t\t} else {\n" - "> +\t\t\tres =3D ad7124_find_closest_match(ad7124_gain,\n" + "> +\t\t\tres = ad7124_find_closest_match(ad7124_gain,\n" "> +\t\t\t\t\t\tARRAY_SIZE(ad7124_gain), tmp);\n" - "> +\t\t\tst->channel_config[channel].pga_bits =3D res;\n" + "> +\t\t\tst->channel_config[channel].pga_bits = res;\n" "Hmm. The old question of what to put in DT as it reflects wiring and\n" "what to leave to userspace. Gain is tricky as only some values make sense\n" "for a given system, but there can be more than one that does...\n" @@ -591,7 +582,7 @@ "\n" "> +\t\t}\n" "> +\n" - "> +\t\tret =3D of_property_read_u32(child, \"adi,odr-hz\", &tmp);\n" + "> +\t\tret = of_property_read_u32(child, \"adi,odr-hz\", &tmp);\n" "\n" "Why is this in DT. This one feels like a userspace choice to me. It's\n" "only tangentially connected to how things are connected on the board.\n" @@ -604,15 +595,15 @@ "> +\t\t\t * 9 SPS is the minimum output data rate supported\n" "> +\t\t\t * regardless of the selected power mode.\n" "> +\t\t\t */\n" - "> +\t\t\tst->channel_config[channel].odr =3D 9;\n" + "> +\t\t\tst->channel_config[channel].odr = 9;\n" "> +\t\telse\n" - "> +\t\t\tst->channel_config[channel].odr =3D tmp;\n" + "> +\t\t\tst->channel_config[channel].odr = tmp;\n" "> +\n" - "> +\t\t*chan =3D ad7124_channel_template;\n" - "> +\t\tchan->address =3D channel;\n" - "> +\t\tchan->scan_index =3D channel;\n" - "> +\t\tchan->channel =3D ain[0];\n" - "> +\t\tchan->channel2 =3D ain[1];\n" + "> +\t\t*chan = ad7124_channel_template;\n" + "> +\t\tchan->address = channel;\n" + "> +\t\tchan->scan_index = channel;\n" + "> +\t\tchan->channel = ain[0];\n" + "> +\t\tchan->channel2 = ain[1];\n" "> +\n" "> +\t\tchan++;\n" "> +\t}\n" @@ -629,46 +620,45 @@ "> +\tunsigned int val, fclk, power_mode;\n" "> +\tint i, ret;\n" "> +\n" - "> +\tfclk =3D clk_get_rate(st->mclk);\n" + "> +\tfclk = clk_get_rate(st->mclk);\n" "> +\tif (!fclk)\n" "> +\t\treturn -EINVAL;\n" "> +\n" "> +\t/* The power mode changes the master clock frequency */\n" - "> +\tpower_mode =3D ad7124_find_closest_match(ad7124_master_clk_freq_hz,\n" + "> +\tpower_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,\n" "> +\t\t\t\t\tARRAY_SIZE(ad7124_master_clk_freq_hz),\n" "> +\t\t\t\t\tfclk);\n" - "> +\tif (fclk !=3D ad7124_master_clk_freq_hz[power_mode]) {\n" - "> +\t\tret =3D clk_set_rate(st->mclk, fclk);\n" + "> +\tif (fclk != ad7124_master_clk_freq_hz[power_mode]) {\n" + "> +\t\tret = clk_set_rate(st->mclk, fclk);\n" "> +\t\tif (ret)\n" "> +\t\t\treturn ret;\n" "> +\t}\n" "> +\n" "> +\t/* Set the power mode */\n" - "> +\tst->adc_control &=3D ~AD7124_ADC_CTRL_PWR_MSK;\n" - "> +\tst->adc_control |=3D AD7124_ADC_CTRL_PWR(power_mode);\n" - "> +\tret =3D ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control=\n" - ");\n" + "> +\tst->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;\n" + "> +\tst->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);\n" + "> +\tret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);\n" "> +\tif (ret < 0)\n" "> +\t\treturn ret;\n" "> +\n" - "> +\tfor (i =3D 0; i < st->num_channels; i++) {\n" - "> +\t\tval =3D st->channel_config[i].ain | AD7124_CHANNEL_SETUP(i);\n" - "> +\t\tret =3D ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, val);\n" + "> +\tfor (i = 0; i < st->num_channels; i++) {\n" + "> +\t\tval = st->channel_config[i].ain | AD7124_CHANNEL_SETUP(i);\n" + "> +\t\tret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, val);\n" "> +\t\tif (ret < 0)\n" "> +\t\t\treturn ret;\n" "> +\n" - "> +\t\tret =3D ad7124_init_channel_vref(st, i);\n" + "> +\t\tret = ad7124_init_channel_vref(st, i);\n" "> +\t\tif (ret < 0)\n" "> +\t\t\treturn ret;\n" "> +\n" - "> +\t\tval =3D AD7124_CONFIG_BIPOLAR(st->channel_config[i].bipolar) |\n" + "> +\t\tval = AD7124_CONFIG_BIPOLAR(st->channel_config[i].bipolar) |\n" "> +\t\t AD7124_CONFIG_REF_SEL(st->channel_config[i].refsel) |\n" "> +\t\t AD7124_CONFIG_PGA(st->channel_config[i].pga_bits);\n" - "> +\t\tret =3D ad_sd_write_reg(&st->sd, AD7124_CONFIG(i), 2, val);\n" + "> +\t\tret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(i), 2, val);\n" "> +\t\tif (ret < 0)\n" "> +\t\t\treturn ret;\n" "> +\n" - "> +\t\tret =3D ad7124_set_channel_odr(st, i, st->channel_config[i].odr);\n" + "> +\t\tret = ad7124_set_channel_odr(st, i, st->channel_config[i].odr);\n" "> +\t\tif (ret < 0)\n" "> +\t\t\treturn ret;\n" "> +\t}\n" @@ -683,66 +673,66 @@ "> +\tstruct iio_dev *indio_dev;\n" "> +\tint i, ret;\n" "> +\n" - "> +\tindio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*st));\n" + "> +\tindio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));\n" "> +\tif (!indio_dev)\n" "> +\t\treturn -ENOMEM;\n" "> +\n" - "> +\tst =3D iio_priv(indio_dev);\n" + "> +\tst = iio_priv(indio_dev);\n" "> +\n" - "> +\tid =3D spi_get_device_id(spi);\n" - "> +\tst->chip_info =3D &ad7124_chip_info_tbl[id->driver_data];\n" + "> +\tid = spi_get_device_id(spi);\n" + "> +\tst->chip_info = &ad7124_chip_info_tbl[id->driver_data];\n" "> +\n" "> +\tad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);\n" "> +\n" "> +\tspi_set_drvdata(spi, indio_dev);\n" "> +\n" - "> +\tindio_dev->dev.parent =3D &spi->dev;\n" - "> +\tindio_dev->name =3D spi_get_device_id(spi)->name;\n" - "> +\tindio_dev->modes =3D INDIO_DIRECT_MODE;\n" - "> +\tindio_dev->info =3D &ad7124_info;\n" + "> +\tindio_dev->dev.parent = &spi->dev;\n" + "> +\tindio_dev->name = spi_get_device_id(spi)->name;\n" + "> +\tindio_dev->modes = INDIO_DIRECT_MODE;\n" + "> +\tindio_dev->info = &ad7124_info;\n" "> +\n" - "> +\tret =3D ad7124_of_parse_channel_config(indio_dev, spi->dev.of_node);\n" + "> +\tret = ad7124_of_parse_channel_config(indio_dev, spi->dev.of_node);\n" "> +\tif (ret < 0)\n" "> +\t\treturn ret;\n" "> +\n" - "> +\tfor (i =3D 0; i < ARRAY_SIZE(st->vref); i++) {\n" - "> +\t\tif (i !=3D AD7124_INT_REF) {\n" - "> +\t\t\tst->vref[i] =3D devm_regulator_get_optional(&spi->dev,\n" + "> +\tfor (i = 0; i < ARRAY_SIZE(st->vref); i++) {\n" + "> +\t\tif (i != AD7124_INT_REF) {\n" + "> +\t\t\tst->vref[i] = devm_regulator_get_optional(&spi->dev,\n" "> +\t\t\t\t\t\t\tad7124_ref_names[i]);\n" - "> +\t\t\tif (PTR_ERR(st->vref[i]) =3D=3D -ENODEV)\n" + "> +\t\t\tif (PTR_ERR(st->vref[i]) == -ENODEV)\n" "> +\t\t\t\tcontinue;\n" "> +\t\t\telse if (IS_ERR(st->vref[i]))\n" "> +\t\t\t\treturn PTR_ERR(st->vref[i]);\n" "> +\n" - "> +\t\t\tret =3D regulator_enable(st->vref[i]);\n" + "> +\t\t\tret = regulator_enable(st->vref[i]);\n" "> +\t\t\tif (ret)\n" "> +\t\t\t\treturn ret;\n" "> +\t\t}\n" "> +\t}\n" "> +\n" - "> +\tst->mclk =3D devm_clk_get(&spi->dev, \"mclk\");\n" + "> +\tst->mclk = devm_clk_get(&spi->dev, \"mclk\");\n" "> +\tif (IS_ERR(st->mclk)) {\n" - "> +\t\tret =3D PTR_ERR(st->mclk);\n" + "> +\t\tret = PTR_ERR(st->mclk);\n" "> +\t\tgoto error_regulator_disable;\n" "> +\t}\n" "> +\n" - "> +\tret =3D clk_prepare_enable(st->mclk);\n" + "> +\tret = clk_prepare_enable(st->mclk);\n" "> +\tif (ret < 0)\n" "> +\t\tgoto error_regulator_disable;\n" "> +\n" - "> +\tret =3D ad7124_soft_reset(st);\n" + "> +\tret = ad7124_soft_reset(st);\n" "> +\tif (ret < 0)\n" "> +\t\tgoto error_clk_disable_unprepare;\n" "> +\n" - "> +\tret =3D ad7124_setup(st);\n" + "> +\tret = ad7124_setup(st);\n" "> +\tif (ret < 0)\n" "> +\t\tgoto error_clk_disable_unprepare;\n" "> +\n" - "> +\tret =3D ad_sd_setup_buffer_and_trigger(indio_dev);\n" + "> +\tret = ad_sd_setup_buffer_and_trigger(indio_dev);\n" "> +\tif (ret < 0)\n" "> +\t\tgoto error_clk_disable_unprepare;\n" "> +\n" - "> +\tret =3D iio_device_register(indio_dev);\n" + "> +\tret = iio_device_register(indio_dev);\n" "> +\tif (ret < 0) {\n" "> +\t\tdev_err(&spi->dev, \"Failed to register iio device\\n\");\n" "> +\t\tgoto error_remove_trigger;\n" @@ -755,7 +745,7 @@ "> +error_clk_disable_unprepare:\n" "> +\tclk_disable_unprepare(st->mclk);\n" "> +error_regulator_disable:\n" - "> +\tfor (i =3D ARRAY_SIZE(st->vref) - 1; i >=3D 0; i--) {\n" + "> +\tfor (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {\n" "> +\t\tif (!IS_ERR_OR_NULL(st->vref[i]))\n" "> +\t\t\tregulator_disable(st->vref[i]);\n" "> +\t}\n" @@ -765,8 +755,8 @@ "> +\n" "> +static int ad7124_remove(struct spi_device *spi)\n" "> +{\n" - "> +\tstruct iio_dev *indio_dev =3D spi_get_drvdata(spi);\n" - "> +\tstruct ad7124_state *st =3D iio_priv(indio_dev);\n" + "> +\tstruct iio_dev *indio_dev = spi_get_drvdata(spi);\n" + "> +\tstruct ad7124_state *st = iio_priv(indio_dev);\n" "> +\tint i;\n" "> +\n" "> +\tiio_device_unregister(indio_dev);\n" @@ -780,7 +770,7 @@ "when reviewing so will always confirm they match.\n" "\n" "> +\n" - "> +\tfor (i =3D ARRAY_SIZE(st->vref) - 1; i >=3D 0; i--) {\n" + "> +\tfor (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {\n" "> +\t\tif (!IS_ERR_OR_NULL(st->vref[i]))\n" "> +\t\t\tregulator_disable(st->vref[i]);\n" "> +\t}\n" @@ -788,28 +778,28 @@ "> +\treturn 0;\n" "> +}\n" "> +\n" - "> +static const struct spi_device_id ad7124_id_table[] =3D {\n" + "> +static const struct spi_device_id ad7124_id_table[] = {\n" "> +\t{ \"ad7124-4\", ID_AD7124_4 },\n" "> +\t{ \"ad7124-8\", ID_AD7124_8 },\n" "> +\t{}\n" "> +};\n" "> +MODULE_DEVICE_TABLE(spi, ad7124_id_table);\n" "> +\n" - "> +static const struct of_device_id ad7124_of_match[] =3D {\n" - "> +\t{ .compatible =3D \"adi,ad7124-4\" },\n" - "> +\t{ .compatible =3D \"adi,ad7124-8\" },\n" + "> +static const struct of_device_id ad7124_of_match[] = {\n" + "> +\t{ .compatible = \"adi,ad7124-4\" },\n" + "> +\t{ .compatible = \"adi,ad7124-8\" },\n" "> +\t{ },\n" "> +};\n" "> +MODULE_DEVICE_TABLE(of, ad7124_of_match);\n" "> +\n" - "> +static struct spi_driver ad71124_driver =3D {\n" - "> +\t.driver =3D {\n" - "> +\t\t.name =3D \"ad7124\",\n" - "> +\t\t.of_match_table =3D ad7124_of_match,\n" + "> +static struct spi_driver ad71124_driver = {\n" + "> +\t.driver = {\n" + "> +\t\t.name = \"ad7124\",\n" + "> +\t\t.of_match_table = ad7124_of_match,\n" "> +\t},\n" - "> +\t.probe =3D ad7124_probe,\n" - "> +\t.remove\t=3D ad7124_remove,\n" - "> +\t.id_table =3D ad7124_id_table,\n" + "> +\t.probe = ad7124_probe,\n" + "> +\t.remove\t= ad7124_remove,\n" + "> +\t.id_table = ad7124_id_table,\n" "> +};\n" "> +module_spi_driver(ad71124_driver);\n" "> +\n" @@ -817,4 +807,4 @@ "> +MODULE_DESCRIPTION(\"Analog Devices AD7124 SPI driver\");\n" "> +MODULE_LICENSE(\"GPL\");" -2e5a333cda3548bec1d5c372aa25d894245d7849ff42a072bd2d0e25daa3be6e +b02b08a3a6bce06abba405913c4f47c3e8982330a59ebea7d20da7ed4f257390
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