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X-Received-From: 192.55.52.115 Subject: [Qemu-arm] [PATCH v5 11/24] hw: acpi: Export and generalize the PCI host AML API X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Zhong , Peter Maydell , Stefano Stabellini , Eduardo Habkost , Rob Bradford , "Michael S. Tsirkin" , Shannon Zhao , Igor Mammedov , qemu-arm@nongnu.org, Marcel Apfelbaum , Paolo Bonzini , Anthony Perard , xen-devel@lists.xenproject.org, Richard Henderson Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: cOSfreilyvjl From: Yang Zhong The AML build routines for the PCI host bridge and the corresponding DSDT addition are neither x86 nor PC machine type specific. We can move them to the architecture agnostic hw/acpi folder, and by carrying all the needed information through a new AcpiPciBus structure, we can make them PC machine type independent. Signed-off-by: Yang Zhong Signed-off-by: Rob Bradford Signed-off-by: Samuel Ortiz --- include/hw/acpi/aml-build.h | 8 ++ hw/acpi/aml-build.c | 157 ++++++++++++++++++++++++++++++++++++ hw/i386/acpi-build.c | 115 ++------------------------ 3 files changed, 173 insertions(+), 107 deletions(-) diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index fde2785b9a..1861e37ebf 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -229,6 +229,12 @@ typedef struct AcpiMcfgInfo { uint32_t mcfg_size; } AcpiMcfgInfo; +typedef struct AcpiPciBus { + PCIBus *pci_bus; + Range *pci_hole; + Range *pci_hole64; +} AcpiPciBus; + typedef struct CrsRangeEntry { uint64_t base; uint64_t limit; @@ -411,6 +417,8 @@ Aml *build_osc_method(uint32_t value); void build_mcfg(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info); Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi); Aml *build_prt(bool is_pci0_prt); +void acpi_dsdt_add_pci_bus(Aml *dsdt, AcpiPciBus *pci_host); +Aml *build_pci_host_bridge(Aml *table, AcpiPciBus *pci_host); void crs_range_set_init(CrsRangeSet *range_set); Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set); void crs_replace_with_free_ranges(GPtrArray *ranges, diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index b8e32f15f7..869ed70db3 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -29,6 +29,19 @@ #include "hw/pci/pci_bus.h" #include "qemu/range.h" #include "hw/pci/pci_bridge.h" +#include "hw/i386/pc.h" +#include "sysemu/tpm.h" +#include "hw/acpi/tpm.h" + +#define PCI_HOST_BRIDGE_CONFIG_ADDR 0xcf8 +#define PCI_HOST_BRIDGE_IO_0_MIN_ADDR 0x0000 +#define PCI_HOST_BRIDGE_IO_0_MAX_ADDR 0x0cf7 +#define PCI_HOST_BRIDGE_IO_1_MIN_ADDR 0x0d00 +#define PCI_HOST_BRIDGE_IO_1_MAX_ADDR 0xffff +#define PCI_VGA_MEM_BASE_ADDR 0x000a0000 +#define PCI_VGA_MEM_MAX_ADDR 0x000bffff +#define IO_0_LEN 0xcf8 +#define VGA_MEM_LEN 0x20000 static GArray *build_alloc_array(void) { @@ -2142,6 +2155,150 @@ Aml *build_prt(bool is_pci0_prt) return method; } +Aml *build_pci_host_bridge(Aml *table, AcpiPciBus *pci_host) +{ + CrsRangeEntry *entry; + Aml *scope, *dev, *crs; + CrsRangeSet crs_range_set; + Range *pci_hole = NULL; + Range *pci_hole64 = NULL; + PCIBus *bus = NULL; + int root_bus_limit = 0xFF; + int i; + + bus = pci_host->pci_bus; + assert(bus); + pci_hole = pci_host->pci_hole; + pci_hole64 = pci_host->pci_hole64; + + crs_range_set_init(&crs_range_set); + QLIST_FOREACH(bus, &bus->child, sibling) { + uint8_t bus_num = pci_bus_num(bus); + uint8_t numa_node = pci_bus_numa_node(bus); + + /* look only for expander root buses */ + if (!pci_bus_is_root(bus)) { + continue; + } + + if (bus_num < root_bus_limit) { + root_bus_limit = bus_num - 1; + } + + scope = aml_scope("\\_SB"); + dev = aml_device("PC%.02X", bus_num); + aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); + aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); + if (pci_bus_is_express(bus)) { + aml_append(dev, aml_name_decl("SUPP", aml_int(0))); + aml_append(dev, aml_name_decl("CTRL", aml_int(0))); + aml_append(dev, build_osc_method(0x1F)); + } + if (numa_node != NUMA_NODE_UNASSIGNED) { + aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); + } + + aml_append(dev, build_prt(false)); + crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); + aml_append(dev, aml_name_decl("_CRS", crs)); + aml_append(scope, dev); + aml_append(table, scope); + } + scope = aml_scope("\\_SB.PCI0"); + /* build PCI0._CRS */ + crs = aml_resource_template(); + /* set the pcie bus num */ + aml_append(crs, + aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, + 0x0000, 0x0, root_bus_limit, + 0x0000, root_bus_limit + 1)); + aml_append(crs, aml_io(AML_DECODE16, PCI_HOST_BRIDGE_CONFIG_ADDR, + PCI_HOST_BRIDGE_CONFIG_ADDR, 0x01, 0x08)); + /* set the io region 0 in pci host bridge */ + aml_append(crs, + aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, + AML_POS_DECODE, AML_ENTIRE_RANGE, + 0x0000, PCI_HOST_BRIDGE_IO_0_MIN_ADDR, + PCI_HOST_BRIDGE_IO_0_MAX_ADDR, 0x0000, IO_0_LEN)); + + /* set the io region 1 in pci host bridge */ + crs_replace_with_free_ranges(crs_range_set.io_ranges, + PCI_HOST_BRIDGE_IO_1_MIN_ADDR, + PCI_HOST_BRIDGE_IO_1_MAX_ADDR); + for (i = 0; i < crs_range_set.io_ranges->len; i++) { + entry = g_ptr_array_index(crs_range_set.io_ranges, i); + aml_append(crs, + aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, + AML_POS_DECODE, AML_ENTIRE_RANGE, + 0x0000, entry->base, entry->limit, + 0x0000, entry->limit - entry->base + 1)); + } + + /* set the vga mem region(0) in pci host bridge */ + aml_append(crs, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_CACHEABLE, AML_READ_WRITE, + 0, PCI_VGA_MEM_BASE_ADDR, PCI_VGA_MEM_MAX_ADDR, + 0, VGA_MEM_LEN)); + + /* set the mem region 1 in pci host bridge */ + crs_replace_with_free_ranges(crs_range_set.mem_ranges, + range_lob(pci_hole), + range_upb(pci_hole)); + for (i = 0; i < crs_range_set.mem_ranges->len; i++) { + entry = g_ptr_array_index(crs_range_set.mem_ranges, i); + aml_append(crs, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, + 0, entry->base, entry->limit, + 0, entry->limit - entry->base + 1)); + } + + /* set the mem region 2 in pci host bridge */ + if (!range_is_empty(pci_hole64)) { + crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, + range_lob(pci_hole64), + range_upb(pci_hole64)); + for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { + entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); + aml_append(crs, + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, + AML_MAX_FIXED, + AML_CACHEABLE, AML_READ_WRITE, + 0, entry->base, entry->limit, + 0, entry->limit - entry->base + 1)); + } + } + + if (TPM_IS_TIS(tpm_find())) { + aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, + TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); + } + + aml_append(scope, aml_name_decl("_CRS", crs)); + crs_range_set_free(&crs_range_set); + return scope; +} + +void acpi_dsdt_add_pci_bus(Aml *dsdt, AcpiPciBus *pci_host) +{ + Aml *dev, *pci_scope; + + dev = aml_device("\\_SB.PCI0"); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); + aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); + aml_append(dev, aml_name_decl("_ADR", aml_int(0))); + aml_append(dev, aml_name_decl("_UID", aml_int(1))); + aml_append(dev, aml_name_decl("SUPP", aml_int(0))); + aml_append(dev, aml_name_decl("CTRL", aml_int(0))); + aml_append(dev, build_osc_method(0x1F)); + aml_append(dsdt, dev); + + pci_scope = build_pci_host_bridge(dsdt, pci_host); + aml_append(dsdt, pci_scope); +} + /* Build rsdt table */ void build_rsdt(GArray *table_data, BIOSLinker *linker, GArray *table_offsets, diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index a5f5f83500..14e2624d14 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1253,16 +1253,11 @@ static void build_piix4_pci_hotplug(Aml *table) static void build_dsdt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm, AcpiMiscInfo *misc, - Range *pci_hole, Range *pci_hole64, + AcpiPciBus *pci_host, MachineState *machine, AcpiConfiguration *acpi_conf) { - CrsRangeEntry *entry; Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; - CrsRangeSet crs_range_set; uint32_t nr_mem = machine->ram_slots; - int root_bus_limit = 0xFF; - PCIBus *bus = NULL; - int i; dsdt = init_aml_allocator(); @@ -1337,104 +1332,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, } aml_append(dsdt, scope); - crs_range_set_init(&crs_range_set); - bus = PC_MACHINE(machine)->bus; - if (bus) { - QLIST_FOREACH(bus, &bus->child, sibling) { - uint8_t bus_num = pci_bus_num(bus); - uint8_t numa_node = pci_bus_numa_node(bus); - - /* look only for expander root buses */ - if (!pci_bus_is_root(bus)) { - continue; - } - - if (bus_num < root_bus_limit) { - root_bus_limit = bus_num - 1; - } - - scope = aml_scope("\\_SB"); - dev = aml_device("PC%.02X", bus_num); - aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); - aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); - aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); - if (pci_bus_is_express(bus)) { - aml_append(dev, build_osc_method(ACPI_OSC_CTRL_PCI_ALL)); - } - - if (numa_node != NUMA_NODE_UNASSIGNED) { - aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); - } - - aml_append(dev, build_prt(false)); - crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); - aml_append(dev, aml_name_decl("_CRS", crs)); - aml_append(scope, dev); - aml_append(dsdt, scope); - } - } - - scope = aml_scope("\\_SB.PCI0"); - /* build PCI0._CRS */ - crs = aml_resource_template(); - aml_append(crs, - aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, - 0x0000, 0x0, root_bus_limit, - 0x0000, root_bus_limit + 1)); - aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); - - aml_append(crs, - aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, - AML_POS_DECODE, AML_ENTIRE_RANGE, - 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); - - crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); - for (i = 0; i < crs_range_set.io_ranges->len; i++) { - entry = g_ptr_array_index(crs_range_set.io_ranges, i); - aml_append(crs, - aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, - AML_POS_DECODE, AML_ENTIRE_RANGE, - 0x0000, entry->base, entry->limit, - 0x0000, entry->limit - entry->base + 1)); - } - - aml_append(crs, - aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, - AML_CACHEABLE, AML_READ_WRITE, - 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); - - crs_replace_with_free_ranges(crs_range_set.mem_ranges, - range_lob(pci_hole), - range_upb(pci_hole)); - for (i = 0; i < crs_range_set.mem_ranges->len; i++) { - entry = g_ptr_array_index(crs_range_set.mem_ranges, i); - aml_append(crs, - aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, - 0, entry->base, entry->limit, - 0, entry->limit - entry->base + 1)); - } - - if (!range_is_empty(pci_hole64)) { - crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, - range_lob(pci_hole64), - range_upb(pci_hole64)); - for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { - entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); - aml_append(crs, - aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, - AML_MAX_FIXED, - AML_CACHEABLE, AML_READ_WRITE, - 0, entry->base, entry->limit, - 0, entry->limit - entry->base + 1)); - } - } - - if (TPM_IS_TIS(tpm_find())) { - aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, - TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); - } - aml_append(scope, aml_name_decl("_CRS", crs)); + scope = build_pci_host_bridge(dsdt, pci_host); /* reserve GPE0 block resources */ dev = aml_device("GPE0"); @@ -1454,8 +1352,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(dev, aml_name_decl("_CRS", crs)); aml_append(scope, dev); - crs_range_set_free(&crs_range_set); - /* reserve PCIHP resources */ if (pm->pcihp_io_len) { dev = aml_device("PHPR"); @@ -2012,6 +1908,11 @@ void acpi_build(AcpiBuildTables *tables, 64 /* Ensure FACS is aligned */, false /* high memory */); + AcpiPciBus pci_host = { + .pci_bus = PC_MACHINE(machine)->bus, + .pci_hole = &pci_hole, + .pci_hole64 = &pci_hole64, + }; /* * FACS is pointed to by FADT. * We place it first since it's the only table that has alignment @@ -2023,7 +1924,7 @@ void acpi_build(AcpiBuildTables *tables, /* DSDT is pointed to by FADT */ dsdt = tables_blob->len; build_dsdt(tables_blob, tables->linker, &pm, &misc, - &pci_hole, &pci_hole64, machine, acpi_conf); + &pci_host, machine, acpi_conf); /* Count the size of the DSDT and SSDT, we will need it for legacy * sizing of ACPI tables. -- 2.19.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Samuel Ortiz Subject: [PATCH v5 11/24] hw: acpi: Export and generalize the PCI host AML API Date: Mon, 5 Nov 2018 02:40:34 +0100 Message-ID: <20181105014047.26447-12-sameo@linux.intel.com> References: <20181105014047.26447-1-sameo@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gJTuY-0003sC-Ig for xen-devel@lists.xenproject.org; Mon, 05 Nov 2018 01:42:38 +0000 In-Reply-To: <20181105014047.26447-1-sameo@linux.intel.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To: qemu-devel@nongnu.org Cc: Yang Zhong , Peter Maydell , Stefano Stabellini , Eduardo Habkost , Rob Bradford , "Michael S. Tsirkin" , Shannon Zhao , Igor Mammedov , qemu-arm@nongnu.org, Marcel Apfelbaum , Paolo Bonzini , Anthony Perard , xen-devel@lists.xenproject.org, Richard Henderson List-Id: xen-devel@lists.xenproject.org RnJvbTogWWFuZyBaaG9uZyA8eWFuZy56aG9uZ0BpbnRlbC5jb20+CgpUaGUgQU1MIGJ1aWxkIHJv dXRpbmVzIGZvciB0aGUgUENJIGhvc3QgYnJpZGdlIGFuZCB0aGUgY29ycmVzcG9uZGluZwpEU0RU IGFkZGl0aW9uIGFyZSBuZWl0aGVyIHg4NiBub3IgUEMgbWFjaGluZSB0eXBlIHNwZWNpZmljLgpX ZSBjYW4gbW92ZSB0aGVtIHRvIHRoZSBhcmNoaXRlY3R1cmUgYWdub3N0aWMgaHcvYWNwaSBmb2xk ZXIsIGFuZCBieQpjYXJyeWluZyBhbGwgdGhlIG5lZWRlZCBpbmZvcm1hdGlvbiB0aHJvdWdoIGEg bmV3IEFjcGlQY2lCdXMgc3RydWN0dXJlLAp3ZSBjYW4gbWFrZSB0aGVtIFBDIG1hY2hpbmUgdHlw ZSBpbmRlcGVuZGVudC4KClNpZ25lZC1vZmYtYnk6IFlhbmcgWmhvbmcgPHlhbmcuemhvbmdAaW50 ZWwuY29tPgpTaWduZWQtb2ZmLWJ5OiBSb2IgQnJhZGZvcmQgPHJvYmVydC5icmFkZm9yZEBpbnRl bC5jb20+ClNpZ25lZC1vZmYtYnk6IFNhbXVlbCBPcnRpeiA8c2FtZW9AbGludXguaW50ZWwuY29t PgotLS0KIGluY2x1ZGUvaHcvYWNwaS9hbWwtYnVpbGQuaCB8ICAgOCArKwogaHcvYWNwaS9hbWwt YnVpbGQuYyAgICAgICAgIHwgMTU3ICsrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysr KwogaHcvaTM4Ni9hY3BpLWJ1aWxkLmMgICAgICAgIHwgMTE1ICsrLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tCiAzIGZpbGVzIGNoYW5nZWQsIDE3MyBpbnNlcnRpb25zKCspLCAxMDcgZGVsZXRpb25z KC0pCgpkaWZmIC0tZ2l0IGEvaW5jbHVkZS9ody9hY3BpL2FtbC1idWlsZC5oIGIvaW5jbHVkZS9o dy9hY3BpL2FtbC1idWlsZC5oCmluZGV4IGZkZTI3ODViOWEuLjE4NjFlMzdlYmYgMTAwNjQ0Ci0t LSBhL2luY2x1ZGUvaHcvYWNwaS9hbWwtYnVpbGQuaAorKysgYi9pbmNsdWRlL2h3L2FjcGkvYW1s LWJ1aWxkLmgKQEAgLTIyOSw2ICsyMjksMTIgQEAgdHlwZWRlZiBzdHJ1Y3QgQWNwaU1jZmdJbmZv IHsKICAgICB1aW50MzJfdCBtY2ZnX3NpemU7CiB9IEFjcGlNY2ZnSW5mbzsKIAordHlwZWRlZiBz dHJ1Y3QgQWNwaVBjaUJ1cyB7CisgICAgUENJQnVzICpwY2lfYnVzOworICAgIFJhbmdlICpwY2lf aG9sZTsKKyAgICBSYW5nZSAqcGNpX2hvbGU2NDsKK30gQWNwaVBjaUJ1czsKKwogdHlwZWRlZiBz dHJ1Y3QgQ3JzUmFuZ2VFbnRyeSB7CiAgICAgdWludDY0X3QgYmFzZTsKICAgICB1aW50NjRfdCBs aW1pdDsKQEAgLTQxMSw2ICs0MTcsOCBAQCBBbWwgKmJ1aWxkX29zY19tZXRob2QodWludDMyX3Qg dmFsdWUpOwogdm9pZCBidWlsZF9tY2ZnKEdBcnJheSAqdGFibGVfZGF0YSwgQklPU0xpbmtlciAq bGlua2VyLCBBY3BpTWNmZ0luZm8gKmluZm8pOwogQW1sICpidWlsZF9nc2lfbGlua19kZXYoY29u c3QgY2hhciAqbmFtZSwgdWludDhfdCB1aWQsIHVpbnQ4X3QgZ3NpKTsKIEFtbCAqYnVpbGRfcHJ0 KGJvb2wgaXNfcGNpMF9wcnQpOwordm9pZCBhY3BpX2RzZHRfYWRkX3BjaV9idXMoQW1sICpkc2R0 LCBBY3BpUGNpQnVzICpwY2lfaG9zdCk7CitBbWwgKmJ1aWxkX3BjaV9ob3N0X2JyaWRnZShBbWwg KnRhYmxlLCBBY3BpUGNpQnVzICpwY2lfaG9zdCk7CiB2b2lkIGNyc19yYW5nZV9zZXRfaW5pdChD cnNSYW5nZVNldCAqcmFuZ2Vfc2V0KTsKIEFtbCAqYnVpbGRfY3JzKFBDSUhvc3RTdGF0ZSAqaG9z dCwgQ3JzUmFuZ2VTZXQgKnJhbmdlX3NldCk7CiB2b2lkIGNyc19yZXBsYWNlX3dpdGhfZnJlZV9y YW5nZXMoR1B0ckFycmF5ICpyYW5nZXMsCmRpZmYgLS1naXQgYS9ody9hY3BpL2FtbC1idWlsZC5j IGIvaHcvYWNwaS9hbWwtYnVpbGQuYwppbmRleCBiOGUzMmYxNWY3Li44NjllZDcwZGIzIDEwMDY0 NAotLS0gYS9ody9hY3BpL2FtbC1idWlsZC5jCisrKyBiL2h3L2FjcGkvYW1sLWJ1aWxkLmMKQEAg LTI5LDYgKzI5LDE5IEBACiAjaW5jbHVkZSAiaHcvcGNpL3BjaV9idXMuaCIKICNpbmNsdWRlICJx ZW11L3JhbmdlLmgiCiAjaW5jbHVkZSAiaHcvcGNpL3BjaV9icmlkZ2UuaCIKKyNpbmNsdWRlICJo dy9pMzg2L3BjLmgiCisjaW5jbHVkZSAic3lzZW11L3RwbS5oIgorI2luY2x1ZGUgImh3L2FjcGkv dHBtLmgiCisKKyNkZWZpbmUgUENJX0hPU1RfQlJJREdFX0NPTkZJR19BRERSICAgICAgICAweGNm OAorI2RlZmluZSBQQ0lfSE9TVF9CUklER0VfSU9fMF9NSU5fQUREUiAgICAgIDB4MDAwMAorI2Rl ZmluZSBQQ0lfSE9TVF9CUklER0VfSU9fMF9NQVhfQUREUiAgICAgIDB4MGNmNworI2RlZmluZSBQ Q0lfSE9TVF9CUklER0VfSU9fMV9NSU5fQUREUiAgICAgIDB4MGQwMAorI2RlZmluZSBQQ0lfSE9T VF9CUklER0VfSU9fMV9NQVhfQUREUiAgICAgIDB4ZmZmZgorI2RlZmluZSBQQ0lfVkdBX01FTV9C QVNFX0FERFIgICAgICAgICAgICAgIDB4MDAwYTAwMDAKKyNkZWZpbmUgUENJX1ZHQV9NRU1fTUFY X0FERFIgICAgICAgICAgICAgICAweDAwMGJmZmZmCisjZGVmaW5lIElPXzBfTEVOICAgICAgICAg ICAgICAgICAgICAgICAgICAgMHhjZjgKKyNkZWZpbmUgVkdBX01FTV9MRU4gICAgICAgICAgICAg ICAgICAgICAgICAweDIwMDAwCiAKIHN0YXRpYyBHQXJyYXkgKmJ1aWxkX2FsbG9jX2FycmF5KHZv aWQpCiB7CkBAIC0yMTQyLDYgKzIxNTUsMTUwIEBAIEFtbCAqYnVpbGRfcHJ0KGJvb2wgaXNfcGNp MF9wcnQpCiAgICAgcmV0dXJuIG1ldGhvZDsKIH0KIAorQW1sICpidWlsZF9wY2lfaG9zdF9icmlk Z2UoQW1sICp0YWJsZSwgQWNwaVBjaUJ1cyAqcGNpX2hvc3QpCit7CisgICAgQ3JzUmFuZ2VFbnRy eSAqZW50cnk7CisgICAgQW1sICpzY29wZSwgKmRldiwgKmNyczsKKyAgICBDcnNSYW5nZVNldCBj cnNfcmFuZ2Vfc2V0OworICAgIFJhbmdlICpwY2lfaG9sZSA9IE5VTEw7CisgICAgUmFuZ2UgKnBj aV9ob2xlNjQgPSBOVUxMOworICAgIFBDSUJ1cyAqYnVzID0gTlVMTDsKKyAgICBpbnQgcm9vdF9i dXNfbGltaXQgPSAweEZGOworICAgIGludCBpOworCisgICAgYnVzID0gcGNpX2hvc3QtPnBjaV9i dXM7CisgICAgYXNzZXJ0KGJ1cyk7CisgICAgcGNpX2hvbGUgPSBwY2lfaG9zdC0+cGNpX2hvbGU7 CisgICAgcGNpX2hvbGU2NCA9IHBjaV9ob3N0LT5wY2lfaG9sZTY0OworCisgICAgY3JzX3Jhbmdl X3NldF9pbml0KCZjcnNfcmFuZ2Vfc2V0KTsKKyAgICBRTElTVF9GT1JFQUNIKGJ1cywgJmJ1cy0+ Y2hpbGQsIHNpYmxpbmcpIHsKKyAgICAgICAgdWludDhfdCBidXNfbnVtID0gcGNpX2J1c19udW0o YnVzKTsKKyAgICAgICAgdWludDhfdCBudW1hX25vZGUgPSBwY2lfYnVzX251bWFfbm9kZShidXMp OworCisgICAgICAgIC8qIGxvb2sgb25seSBmb3IgZXhwYW5kZXIgcm9vdCBidXNlcyAqLworICAg ICAgICBpZiAoIXBjaV9idXNfaXNfcm9vdChidXMpKSB7CisgICAgICAgICAgICBjb250aW51ZTsK KyAgICAgICAgfQorCisgICAgICAgIGlmIChidXNfbnVtIDwgcm9vdF9idXNfbGltaXQpIHsKKyAg ICAgICAgICAgIHJvb3RfYnVzX2xpbWl0ID0gYnVzX251bSAtIDE7CisgICAgICAgIH0KKworICAg ICAgICBzY29wZSA9IGFtbF9zY29wZSgiXFxfU0IiKTsKKyAgICAgICAgZGV2ID0gYW1sX2Rldmlj ZSgiUEMlLjAyWCIsIGJ1c19udW0pOworICAgICAgICBhbWxfYXBwZW5kKGRldiwgYW1sX25hbWVf ZGVjbCgiX1VJRCIsIGFtbF9pbnQoYnVzX251bSkpKTsKKyAgICAgICAgYW1sX2FwcGVuZChkZXYs IGFtbF9uYW1lX2RlY2woIl9ISUQiLCBhbWxfZWlzYWlkKCJQTlAwQTAzIikpKTsKKyAgICAgICAg YW1sX2FwcGVuZChkZXYsIGFtbF9uYW1lX2RlY2woIl9CQk4iLCBhbWxfaW50KGJ1c19udW0pKSk7 CisgICAgICAgIGlmIChwY2lfYnVzX2lzX2V4cHJlc3MoYnVzKSkgeworICAgICAgICAgICAgYW1s X2FwcGVuZChkZXYsIGFtbF9uYW1lX2RlY2woIlNVUFAiLCBhbWxfaW50KDApKSk7CisgICAgICAg ICAgICBhbWxfYXBwZW5kKGRldiwgYW1sX25hbWVfZGVjbCgiQ1RSTCIsIGFtbF9pbnQoMCkpKTsK KyAgICAgICAgICAgIGFtbF9hcHBlbmQoZGV2LCBidWlsZF9vc2NfbWV0aG9kKDB4MUYpKTsKKyAg ICAgICAgfQorICAgICAgICBpZiAobnVtYV9ub2RlICE9IE5VTUFfTk9ERV9VTkFTU0lHTkVEKSB7 CisgICAgICAgICAgICBhbWxfYXBwZW5kKGRldiwgYW1sX25hbWVfZGVjbCgiX1BYTSIsIGFtbF9p bnQobnVtYV9ub2RlKSkpOworICAgICAgICB9CisKKyAgICAgICAgYW1sX2FwcGVuZChkZXYsIGJ1 aWxkX3BydChmYWxzZSkpOworICAgICAgICBjcnMgPSBidWlsZF9jcnMoUENJX0hPU1RfQlJJREdF KEJVUyhidXMpLT5wYXJlbnQpLCAmY3JzX3JhbmdlX3NldCk7CisgICAgICAgIGFtbF9hcHBlbmQo ZGV2LCBhbWxfbmFtZV9kZWNsKCJfQ1JTIiwgY3JzKSk7CisgICAgICAgIGFtbF9hcHBlbmQoc2Nv cGUsIGRldik7CisgICAgICAgIGFtbF9hcHBlbmQodGFibGUsIHNjb3BlKTsKKyAgICB9CisgICAg c2NvcGUgPSBhbWxfc2NvcGUoIlxcX1NCLlBDSTAiKTsKKyAgICAvKiBidWlsZCBQQ0kwLl9DUlMg Ki8KKyAgICBjcnMgPSBhbWxfcmVzb3VyY2VfdGVtcGxhdGUoKTsKKyAgICAvKiBzZXQgdGhlIHBj aWUgYnVzIG51bSAqLworICAgIGFtbF9hcHBlbmQoY3JzLAorICAgICAgICBhbWxfd29yZF9idXNf bnVtYmVyKEFNTF9NSU5fRklYRUQsIEFNTF9NQVhfRklYRUQsIEFNTF9QT1NfREVDT0RFLAorICAg ICAgICAgICAgICAgICAgICAgICAgICAgIDB4MDAwMCwgMHgwLCByb290X2J1c19saW1pdCwKKyAg ICAgICAgICAgICAgICAgICAgICAgICAgICAweDAwMDAsIHJvb3RfYnVzX2xpbWl0ICsgMSkpOwor ICAgIGFtbF9hcHBlbmQoY3JzLCBhbWxfaW8oQU1MX0RFQ09ERTE2LCBQQ0lfSE9TVF9CUklER0Vf Q09ORklHX0FERFIsCisgICAgICAgICAgICAgICAgICAgICAgICAgICBQQ0lfSE9TVF9CUklER0Vf Q09ORklHX0FERFIsIDB4MDEsIDB4MDgpKTsKKyAgICAvKiBzZXQgdGhlIGlvIHJlZ2lvbiAwIGlu IHBjaSBob3N0IGJyaWRnZSAqLworICAgIGFtbF9hcHBlbmQoY3JzLAorICAgICAgICBhbWxfd29y ZF9pbyhBTUxfTUlOX0ZJWEVELCBBTUxfTUFYX0ZJWEVELAorICAgICAgICAgICAgICAgICAgICBB TUxfUE9TX0RFQ09ERSwgQU1MX0VOVElSRV9SQU5HRSwKKyAgICAgICAgICAgICAgICAgICAgMHgw MDAwLCBQQ0lfSE9TVF9CUklER0VfSU9fMF9NSU5fQUREUiwKKyAgICAgICAgICAgICAgICAgICAg UENJX0hPU1RfQlJJREdFX0lPXzBfTUFYX0FERFIsIDB4MDAwMCwgSU9fMF9MRU4pKTsKKworICAg IC8qIHNldCB0aGUgaW8gcmVnaW9uIDEgaW4gcGNpIGhvc3QgYnJpZGdlICovCisgICAgY3JzX3Jl cGxhY2Vfd2l0aF9mcmVlX3JhbmdlcyhjcnNfcmFuZ2Vfc2V0LmlvX3JhbmdlcywKKyAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgIFBDSV9IT1NUX0JSSURHRV9JT18xX01JTl9BRERSLAor ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgUENJX0hPU1RfQlJJREdFX0lPXzFfTUFY X0FERFIpOworICAgIGZvciAoaSA9IDA7IGkgPCBjcnNfcmFuZ2Vfc2V0LmlvX3Jhbmdlcy0+bGVu OyBpKyspIHsKKyAgICAgICAgZW50cnkgPSBnX3B0cl9hcnJheV9pbmRleChjcnNfcmFuZ2Vfc2V0 LmlvX3JhbmdlcywgaSk7CisgICAgICAgIGFtbF9hcHBlbmQoY3JzLAorICAgICAgICAgICAgYW1s X3dvcmRfaW8oQU1MX01JTl9GSVhFRCwgQU1MX01BWF9GSVhFRCwKKyAgICAgICAgICAgICAgICAg ICAgICAgIEFNTF9QT1NfREVDT0RFLCBBTUxfRU5USVJFX1JBTkdFLAorICAgICAgICAgICAgICAg ICAgICAgICAgMHgwMDAwLCBlbnRyeS0+YmFzZSwgZW50cnktPmxpbWl0LAorICAgICAgICAgICAg ICAgICAgICAgICAgMHgwMDAwLCBlbnRyeS0+bGltaXQgLSBlbnRyeS0+YmFzZSArIDEpKTsKKyAg ICB9CisKKyAgICAvKiBzZXQgdGhlIHZnYSBtZW0gcmVnaW9uKDApIGluIHBjaSBob3N0IGJyaWRn ZSAqLworICAgIGFtbF9hcHBlbmQoY3JzLAorICAgICAgICBhbWxfZHdvcmRfbWVtb3J5KEFNTF9Q T1NfREVDT0RFLCBBTUxfTUlOX0ZJWEVELCBBTUxfTUFYX0ZJWEVELAorICAgICAgICAgICAgICAg ICAgICAgICAgIEFNTF9DQUNIRUFCTEUsIEFNTF9SRUFEX1dSSVRFLAorICAgICAgICAgICAgICAg ICAgICAgICAgIDAsIFBDSV9WR0FfTUVNX0JBU0VfQUREUiwgUENJX1ZHQV9NRU1fTUFYX0FERFIs CisgICAgICAgICAgICAgICAgICAgICAgICAgMCwgVkdBX01FTV9MRU4pKTsKKworICAgIC8qIHNl dCB0aGUgbWVtIHJlZ2lvbiAxIGluIHBjaSBob3N0IGJyaWRnZSAqLworICAgIGNyc19yZXBsYWNl X3dpdGhfZnJlZV9yYW5nZXMoY3JzX3JhbmdlX3NldC5tZW1fcmFuZ2VzLAorICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgcmFuZ2VfbG9iKHBjaV9ob2xlKSwKKyAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgIHJhbmdlX3VwYihwY2lfaG9sZSkpOworICAgIGZvciAoaSA9IDA7 IGkgPCBjcnNfcmFuZ2Vfc2V0Lm1lbV9yYW5nZXMtPmxlbjsgaSsrKSB7CisgICAgICAgIGVudHJ5 ID0gZ19wdHJfYXJyYXlfaW5kZXgoY3JzX3JhbmdlX3NldC5tZW1fcmFuZ2VzLCBpKTsKKyAgICAg ICAgYW1sX2FwcGVuZChjcnMsCisgICAgICAgICAgICBhbWxfZHdvcmRfbWVtb3J5KEFNTF9QT1Nf REVDT0RFLCBBTUxfTUlOX0ZJWEVELCBBTUxfTUFYX0ZJWEVELAorICAgICAgICAgICAgICAgICAg ICAgICAgICAgICBBTUxfTk9OX0NBQ0hFQUJMRSwgQU1MX1JFQURfV1JJVEUsCisgICAgICAgICAg ICAgICAgICAgICAgICAgICAgIDAsIGVudHJ5LT5iYXNlLCBlbnRyeS0+bGltaXQsCisgICAgICAg ICAgICAgICAgICAgICAgICAgICAgIDAsIGVudHJ5LT5saW1pdCAtIGVudHJ5LT5iYXNlICsgMSkp OworICAgIH0KKworICAgIC8qIHNldCB0aGUgbWVtIHJlZ2lvbiAyIGluIHBjaSBob3N0IGJyaWRn ZSAqLworICAgIGlmICghcmFuZ2VfaXNfZW1wdHkocGNpX2hvbGU2NCkpIHsKKyAgICAgICAgY3Jz X3JlcGxhY2Vfd2l0aF9mcmVlX3JhbmdlcyhjcnNfcmFuZ2Vfc2V0Lm1lbV82NGJpdF9yYW5nZXMs CisgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgcmFuZ2VfbG9iKHBjaV9ob2xl NjQpLAorICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHJhbmdlX3VwYihwY2lf aG9sZTY0KSk7CisgICAgICAgIGZvciAoaSA9IDA7IGkgPCBjcnNfcmFuZ2Vfc2V0Lm1lbV82NGJp dF9yYW5nZXMtPmxlbjsgaSsrKSB7CisgICAgICAgICAgICBlbnRyeSA9IGdfcHRyX2FycmF5X2lu ZGV4KGNyc19yYW5nZV9zZXQubWVtXzY0Yml0X3JhbmdlcywgaSk7CisgICAgICAgICAgICBhbWxf YXBwZW5kKGNycywKKyAgICAgICAgICAgICAgICAgICAgICAgYW1sX3F3b3JkX21lbW9yeShBTUxf UE9TX0RFQ09ERSwgQU1MX01JTl9GSVhFRCwKKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICBBTUxfTUFYX0ZJWEVELAorICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgIEFNTF9DQUNIRUFCTEUsIEFNTF9SRUFEX1dSSVRFLAorICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgIDAsIGVudHJ5LT5iYXNlLCBlbnRyeS0+bGltaXQsCisg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgMCwgZW50cnktPmxpbWl0IC0g ZW50cnktPmJhc2UgKyAxKSk7CisgICAgICAgIH0KKyAgICB9CisKKyAgICBpZiAoVFBNX0lTX1RJ Uyh0cG1fZmluZCgpKSkgeworICAgICAgICBhbWxfYXBwZW5kKGNycywgYW1sX21lbW9yeTMyX2Zp eGVkKFRQTV9USVNfQUREUl9CQVNFLAorICAgICAgICAgICAgICAgICAgIFRQTV9USVNfQUREUl9T SVpFLCBBTUxfUkVBRF9XUklURSkpOworICAgIH0KKworICAgIGFtbF9hcHBlbmQoc2NvcGUsIGFt bF9uYW1lX2RlY2woIl9DUlMiLCBjcnMpKTsKKyAgICBjcnNfcmFuZ2Vfc2V0X2ZyZWUoJmNyc19y YW5nZV9zZXQpOworICAgIHJldHVybiBzY29wZTsKK30KKwordm9pZCBhY3BpX2RzZHRfYWRkX3Bj aV9idXMoQW1sICpkc2R0LCBBY3BpUGNpQnVzICpwY2lfaG9zdCkKK3sKKyAgICBBbWwgKmRldiwg KnBjaV9zY29wZTsKKworICAgIGRldiA9IGFtbF9kZXZpY2UoIlxcX1NCLlBDSTAiKTsKKyAgICBh bWxfYXBwZW5kKGRldiwgYW1sX25hbWVfZGVjbCgiX0hJRCIsIGFtbF9laXNhaWQoIlBOUDBBMDgi KSkpOworICAgIGFtbF9hcHBlbmQoZGV2LCBhbWxfbmFtZV9kZWNsKCJfQ0lEIiwgYW1sX2Vpc2Fp ZCgiUE5QMEEwMyIpKSk7CisgICAgYW1sX2FwcGVuZChkZXYsIGFtbF9uYW1lX2RlY2woIl9BRFIi LCBhbWxfaW50KDApKSk7CisgICAgYW1sX2FwcGVuZChkZXYsIGFtbF9uYW1lX2RlY2woIl9VSUQi LCBhbWxfaW50KDEpKSk7CisgICAgYW1sX2FwcGVuZChkZXYsIGFtbF9uYW1lX2RlY2woIlNVUFAi LCBhbWxfaW50KDApKSk7CisgICAgYW1sX2FwcGVuZChkZXYsIGFtbF9uYW1lX2RlY2woIkNUUkwi LCBhbWxfaW50KDApKSk7CisgICAgYW1sX2FwcGVuZChkZXYsIGJ1aWxkX29zY19tZXRob2QoMHgx RikpOworICAgIGFtbF9hcHBlbmQoZHNkdCwgZGV2KTsKKworICAgIHBjaV9zY29wZSA9IGJ1aWxk X3BjaV9ob3N0X2JyaWRnZShkc2R0LCBwY2lfaG9zdCk7CisgICAgYW1sX2FwcGVuZChkc2R0LCBw Y2lfc2NvcGUpOworfQorCiAvKiBCdWlsZCByc2R0IHRhYmxlICovCiB2b2lkCiBidWlsZF9yc2R0 KEdBcnJheSAqdGFibGVfZGF0YSwgQklPU0xpbmtlciAqbGlua2VyLCBHQXJyYXkgKnRhYmxlX29m ZnNldHMsCmRpZmYgLS1naXQgYS9ody9pMzg2L2FjcGktYnVpbGQuYyBiL2h3L2kzODYvYWNwaS1i dWlsZC5jCmluZGV4IGE1ZjVmODM1MDAuLjE0ZTI2MjRkMTQgMTAwNjQ0Ci0tLSBhL2h3L2kzODYv YWNwaS1idWlsZC5jCisrKyBiL2h3L2kzODYvYWNwaS1idWlsZC5jCkBAIC0xMjUzLDE2ICsxMjUz LDExIEBAIHN0YXRpYyB2b2lkIGJ1aWxkX3BpaXg0X3BjaV9ob3RwbHVnKEFtbCAqdGFibGUpCiBz dGF0aWMgdm9pZAogYnVpbGRfZHNkdChHQXJyYXkgKnRhYmxlX2RhdGEsIEJJT1NMaW5rZXIgKmxp bmtlciwKICAgICAgICAgICAgQWNwaVBtSW5mbyAqcG0sIEFjcGlNaXNjSW5mbyAqbWlzYywKLSAg ICAgICAgICAgUmFuZ2UgKnBjaV9ob2xlLCBSYW5nZSAqcGNpX2hvbGU2NCwKKyAgICAgICAgICAg QWNwaVBjaUJ1cyAqcGNpX2hvc3QsCiAgICAgICAgICAgIE1hY2hpbmVTdGF0ZSAqbWFjaGluZSwg QWNwaUNvbmZpZ3VyYXRpb24gKmFjcGlfY29uZikKIHsKLSAgICBDcnNSYW5nZUVudHJ5ICplbnRy eTsKICAgICBBbWwgKmRzZHQsICpzYl9zY29wZSwgKnNjb3BlLCAqZGV2LCAqbWV0aG9kLCAqZmll bGQsICpwa2csICpjcnM7Ci0gICAgQ3JzUmFuZ2VTZXQgY3JzX3JhbmdlX3NldDsKICAgICB1aW50 MzJfdCBucl9tZW0gPSBtYWNoaW5lLT5yYW1fc2xvdHM7Ci0gICAgaW50IHJvb3RfYnVzX2xpbWl0 ID0gMHhGRjsKLSAgICBQQ0lCdXMgKmJ1cyA9IE5VTEw7Ci0gICAgaW50IGk7CiAKICAgICBkc2R0 ID0gaW5pdF9hbWxfYWxsb2NhdG9yKCk7CiAKQEAgLTEzMzcsMTA0ICsxMzMyLDcgQEAgYnVpbGRf ZHNkdChHQXJyYXkgKnRhYmxlX2RhdGEsIEJJT1NMaW5rZXIgKmxpbmtlciwKICAgICB9CiAgICAg YW1sX2FwcGVuZChkc2R0LCBzY29wZSk7CiAKLSAgICBjcnNfcmFuZ2Vfc2V0X2luaXQoJmNyc19y YW5nZV9zZXQpOwotICAgIGJ1cyA9IFBDX01BQ0hJTkUobWFjaGluZSktPmJ1czsKLSAgICBpZiAo YnVzKSB7Ci0gICAgICAgIFFMSVNUX0ZPUkVBQ0goYnVzLCAmYnVzLT5jaGlsZCwgc2libGluZykg ewotICAgICAgICAgICAgdWludDhfdCBidXNfbnVtID0gcGNpX2J1c19udW0oYnVzKTsKLSAgICAg ICAgICAgIHVpbnQ4X3QgbnVtYV9ub2RlID0gcGNpX2J1c19udW1hX25vZGUoYnVzKTsKLQotICAg ICAgICAgICAgLyogbG9vayBvbmx5IGZvciBleHBhbmRlciByb290IGJ1c2VzICovCi0gICAgICAg ICAgICBpZiAoIXBjaV9idXNfaXNfcm9vdChidXMpKSB7Ci0gICAgICAgICAgICAgICAgY29udGlu dWU7Ci0gICAgICAgICAgICB9Ci0KLSAgICAgICAgICAgIGlmIChidXNfbnVtIDwgcm9vdF9idXNf bGltaXQpIHsKLSAgICAgICAgICAgICAgICByb290X2J1c19saW1pdCA9IGJ1c19udW0gLSAxOwot ICAgICAgICAgICAgfQotCi0gICAgICAgICAgICBzY29wZSA9IGFtbF9zY29wZSgiXFxfU0IiKTsK LSAgICAgICAgICAgIGRldiA9IGFtbF9kZXZpY2UoIlBDJS4wMlgiLCBidXNfbnVtKTsKLSAgICAg ICAgICAgIGFtbF9hcHBlbmQoZGV2LCBhbWxfbmFtZV9kZWNsKCJfVUlEIiwgYW1sX2ludChidXNf bnVtKSkpOwotICAgICAgICAgICAgYW1sX2FwcGVuZChkZXYsIGFtbF9uYW1lX2RlY2woIl9ISUQi LCBhbWxfZWlzYWlkKCJQTlAwQTAzIikpKTsKLSAgICAgICAgICAgIGFtbF9hcHBlbmQoZGV2LCBh bWxfbmFtZV9kZWNsKCJfQkJOIiwgYW1sX2ludChidXNfbnVtKSkpOwotICAgICAgICAgICAgaWYg KHBjaV9idXNfaXNfZXhwcmVzcyhidXMpKSB7Ci0gICAgICAgICAgICAgICAgYW1sX2FwcGVuZChk ZXYsIGJ1aWxkX29zY19tZXRob2QoQUNQSV9PU0NfQ1RSTF9QQ0lfQUxMKSk7Ci0gICAgICAgICAg ICB9Ci0KLSAgICAgICAgICAgIGlmIChudW1hX25vZGUgIT0gTlVNQV9OT0RFX1VOQVNTSUdORUQp IHsKLSAgICAgICAgICAgICAgICBhbWxfYXBwZW5kKGRldiwgYW1sX25hbWVfZGVjbCgiX1BYTSIs IGFtbF9pbnQobnVtYV9ub2RlKSkpOwotICAgICAgICAgICAgfQotCi0gICAgICAgICAgICBhbWxf YXBwZW5kKGRldiwgYnVpbGRfcHJ0KGZhbHNlKSk7Ci0gICAgICAgICAgICBjcnMgPSBidWlsZF9j cnMoUENJX0hPU1RfQlJJREdFKEJVUyhidXMpLT5wYXJlbnQpLCAmY3JzX3JhbmdlX3NldCk7Ci0g ICAgICAgICAgICBhbWxfYXBwZW5kKGRldiwgYW1sX25hbWVfZGVjbCgiX0NSUyIsIGNycykpOwot ICAgICAgICAgICAgYW1sX2FwcGVuZChzY29wZSwgZGV2KTsKLSAgICAgICAgICAgIGFtbF9hcHBl bmQoZHNkdCwgc2NvcGUpOwotICAgICAgICB9Ci0gICAgfQotCi0gICAgc2NvcGUgPSBhbWxfc2Nv cGUoIlxcX1NCLlBDSTAiKTsKLSAgICAvKiBidWlsZCBQQ0kwLl9DUlMgKi8KLSAgICBjcnMgPSBh bWxfcmVzb3VyY2VfdGVtcGxhdGUoKTsKLSAgICBhbWxfYXBwZW5kKGNycywKLSAgICAgICAgYW1s X3dvcmRfYnVzX251bWJlcihBTUxfTUlOX0ZJWEVELCBBTUxfTUFYX0ZJWEVELCBBTUxfUE9TX0RF Q09ERSwKLSAgICAgICAgICAgICAgICAgICAgICAgICAgICAweDAwMDAsIDB4MCwgcm9vdF9idXNf bGltaXQsCi0gICAgICAgICAgICAgICAgICAgICAgICAgICAgMHgwMDAwLCByb290X2J1c19saW1p dCArIDEpKTsKLSAgICBhbWxfYXBwZW5kKGNycywgYW1sX2lvKEFNTF9ERUNPREUxNiwgMHgwQ0Y4 LCAweDBDRjgsIDB4MDEsIDB4MDgpKTsKLQotICAgIGFtbF9hcHBlbmQoY3JzLAotICAgICAgICBh bWxfd29yZF9pbyhBTUxfTUlOX0ZJWEVELCBBTUxfTUFYX0ZJWEVELAotICAgICAgICAgICAgICAg ICAgICBBTUxfUE9TX0RFQ09ERSwgQU1MX0VOVElSRV9SQU5HRSwKLSAgICAgICAgICAgICAgICAg ICAgMHgwMDAwLCAweDAwMDAsIDB4MENGNywgMHgwMDAwLCAweDBDRjgpKTsKLQotICAgIGNyc19y ZXBsYWNlX3dpdGhfZnJlZV9yYW5nZXMoY3JzX3JhbmdlX3NldC5pb19yYW5nZXMsIDB4MEQwMCwg MHhGRkZGKTsKLSAgICBmb3IgKGkgPSAwOyBpIDwgY3JzX3JhbmdlX3NldC5pb19yYW5nZXMtPmxl bjsgaSsrKSB7Ci0gICAgICAgIGVudHJ5ID0gZ19wdHJfYXJyYXlfaW5kZXgoY3JzX3JhbmdlX3Nl dC5pb19yYW5nZXMsIGkpOwotICAgICAgICBhbWxfYXBwZW5kKGNycywKLSAgICAgICAgICAgIGFt bF93b3JkX2lvKEFNTF9NSU5fRklYRUQsIEFNTF9NQVhfRklYRUQsCi0gICAgICAgICAgICAgICAg ICAgICAgICBBTUxfUE9TX0RFQ09ERSwgQU1MX0VOVElSRV9SQU5HRSwKLSAgICAgICAgICAgICAg ICAgICAgICAgIDB4MDAwMCwgZW50cnktPmJhc2UsIGVudHJ5LT5saW1pdCwKLSAgICAgICAgICAg ICAgICAgICAgICAgIDB4MDAwMCwgZW50cnktPmxpbWl0IC0gZW50cnktPmJhc2UgKyAxKSk7Ci0g ICAgfQotCi0gICAgYW1sX2FwcGVuZChjcnMsCi0gICAgICAgIGFtbF9kd29yZF9tZW1vcnkoQU1M X1BPU19ERUNPREUsIEFNTF9NSU5fRklYRUQsIEFNTF9NQVhfRklYRUQsCi0gICAgICAgICAgICAg ICAgICAgICAgICAgQU1MX0NBQ0hFQUJMRSwgQU1MX1JFQURfV1JJVEUsCi0gICAgICAgICAgICAg ICAgICAgICAgICAgMCwgMHgwMDBBMDAwMCwgMHgwMDBCRkZGRiwgMCwgMHgwMDAyMDAwMCkpOwot Ci0gICAgY3JzX3JlcGxhY2Vfd2l0aF9mcmVlX3JhbmdlcyhjcnNfcmFuZ2Vfc2V0Lm1lbV9yYW5n ZXMsCi0gICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICByYW5nZV9sb2IocGNpX2hvbGUp LAotICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgcmFuZ2VfdXBiKHBjaV9ob2xlKSk7 Ci0gICAgZm9yIChpID0gMDsgaSA8IGNyc19yYW5nZV9zZXQubWVtX3Jhbmdlcy0+bGVuOyBpKysp IHsKLSAgICAgICAgZW50cnkgPSBnX3B0cl9hcnJheV9pbmRleChjcnNfcmFuZ2Vfc2V0Lm1lbV9y YW5nZXMsIGkpOwotICAgICAgICBhbWxfYXBwZW5kKGNycywKLSAgICAgICAgICAgIGFtbF9kd29y ZF9tZW1vcnkoQU1MX1BPU19ERUNPREUsIEFNTF9NSU5fRklYRUQsIEFNTF9NQVhfRklYRUQsCi0g ICAgICAgICAgICAgICAgICAgICAgICAgICAgIEFNTF9OT05fQ0FDSEVBQkxFLCBBTUxfUkVBRF9X UklURSwKLSAgICAgICAgICAgICAgICAgICAgICAgICAgICAgMCwgZW50cnktPmJhc2UsIGVudHJ5 LT5saW1pdCwKLSAgICAgICAgICAgICAgICAgICAgICAgICAgICAgMCwgZW50cnktPmxpbWl0IC0g ZW50cnktPmJhc2UgKyAxKSk7Ci0gICAgfQotCi0gICAgaWYgKCFyYW5nZV9pc19lbXB0eShwY2lf aG9sZTY0KSkgewotICAgICAgICBjcnNfcmVwbGFjZV93aXRoX2ZyZWVfcmFuZ2VzKGNyc19yYW5n ZV9zZXQubWVtXzY0Yml0X3JhbmdlcywKLSAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICByYW5nZV9sb2IocGNpX2hvbGU2NCksCi0gICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgcmFuZ2VfdXBiKHBjaV9ob2xlNjQpKTsKLSAgICAgICAgZm9yIChpID0gMDsgaSA8 IGNyc19yYW5nZV9zZXQubWVtXzY0Yml0X3Jhbmdlcy0+bGVuOyBpKyspIHsKLSAgICAgICAgICAg IGVudHJ5ID0gZ19wdHJfYXJyYXlfaW5kZXgoY3JzX3JhbmdlX3NldC5tZW1fNjRiaXRfcmFuZ2Vz LCBpKTsKLSAgICAgICAgICAgIGFtbF9hcHBlbmQoY3JzLAotICAgICAgICAgICAgICAgICAgICAg ICBhbWxfcXdvcmRfbWVtb3J5KEFNTF9QT1NfREVDT0RFLCBBTUxfTUlOX0ZJWEVELAotICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIEFNTF9NQVhfRklYRUQsCi0gICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgQU1MX0NBQ0hFQUJMRSwgQU1MX1JFQURf V1JJVEUsCi0gICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgMCwgZW50cnkt PmJhc2UsIGVudHJ5LT5saW1pdCwKLSAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAwLCBlbnRyeS0+bGltaXQgLSBlbnRyeS0+YmFzZSArIDEpKTsKLSAgICAgICAgfQotICAg IH0KLQotICAgIGlmIChUUE1fSVNfVElTKHRwbV9maW5kKCkpKSB7Ci0gICAgICAgIGFtbF9hcHBl bmQoY3JzLCBhbWxfbWVtb3J5MzJfZml4ZWQoVFBNX1RJU19BRERSX0JBU0UsCi0gICAgICAgICAg ICAgICAgICAgVFBNX1RJU19BRERSX1NJWkUsIEFNTF9SRUFEX1dSSVRFKSk7Ci0gICAgfQotICAg IGFtbF9hcHBlbmQoc2NvcGUsIGFtbF9uYW1lX2RlY2woIl9DUlMiLCBjcnMpKTsKKyAgICBzY29w ZSA9IGJ1aWxkX3BjaV9ob3N0X2JyaWRnZShkc2R0LCBwY2lfaG9zdCk7CiAKICAgICAvKiByZXNl cnZlIEdQRTAgYmxvY2sgcmVzb3VyY2VzICovCiAgICAgZGV2ID0gYW1sX2RldmljZSgiR1BFMCIp OwpAQCAtMTQ1NCw4ICsxMzUyLDYgQEAgYnVpbGRfZHNkdChHQXJyYXkgKnRhYmxlX2RhdGEsIEJJ T1NMaW5rZXIgKmxpbmtlciwKICAgICBhbWxfYXBwZW5kKGRldiwgYW1sX25hbWVfZGVjbCgiX0NS UyIsIGNycykpOwogICAgIGFtbF9hcHBlbmQoc2NvcGUsIGRldik7CiAKLSAgICBjcnNfcmFuZ2Vf c2V0X2ZyZWUoJmNyc19yYW5nZV9zZXQpOwotCiAgICAgLyogcmVzZXJ2ZSBQQ0lIUCByZXNvdXJj ZXMgKi8KICAgICBpZiAocG0tPnBjaWhwX2lvX2xlbikgewogICAgICAgICBkZXYgPSBhbWxfZGV2 aWNlKCJQSFBSIik7CkBAIC0yMDEyLDYgKzE5MDgsMTEgQEAgdm9pZCBhY3BpX2J1aWxkKEFjcGlC dWlsZFRhYmxlcyAqdGFibGVzLAogICAgICAgICAgICAgICAgICAgICAgICAgICAgICA2NCAvKiBF bnN1cmUgRkFDUyBpcyBhbGlnbmVkICovLAogICAgICAgICAgICAgICAgICAgICAgICAgICAgICBm YWxzZSAvKiBoaWdoIG1lbW9yeSAqLyk7CiAKKyAgICBBY3BpUGNpQnVzIHBjaV9ob3N0ID0gewor ICAgICAgICAucGNpX2J1cyAgICA9IFBDX01BQ0hJTkUobWFjaGluZSktPmJ1cywKKyAgICAgICAg LnBjaV9ob2xlICAgPSAmcGNpX2hvbGUsCisgICAgICAgIC5wY2lfaG9sZTY0ID0gJnBjaV9ob2xl NjQsCisgICAgfTsKICAgICAvKgogICAgICAqIEZBQ1MgaXMgcG9pbnRlZCB0byBieSBGQURULgog ICAgICAqIFdlIHBsYWNlIGl0IGZpcnN0IHNpbmNlIGl0J3MgdGhlIG9ubHkgdGFibGUgdGhhdCBo YXMgYWxpZ25tZW50CkBAIC0yMDIzLDcgKzE5MjQsNyBAQCB2b2lkIGFjcGlfYnVpbGQoQWNwaUJ1 aWxkVGFibGVzICp0YWJsZXMsCiAgICAgLyogRFNEVCBpcyBwb2ludGVkIHRvIGJ5IEZBRFQgKi8K ICAgICBkc2R0ID0gdGFibGVzX2Jsb2ItPmxlbjsKICAgICBidWlsZF9kc2R0KHRhYmxlc19ibG9i LCB0YWJsZXMtPmxpbmtlciwgJnBtLCAmbWlzYywKLSAgICAgICAgICAgICAgICZwY2lfaG9sZSwg JnBjaV9ob2xlNjQsIG1hY2hpbmUsIGFjcGlfY29uZik7CisgICAgICAgICAgICAgICAmcGNpX2hv c3QsIG1hY2hpbmUsIGFjcGlfY29uZik7CiAKICAgICAvKiBDb3VudCB0aGUgc2l6ZSBvZiB0aGUg RFNEVCBhbmQgU1NEVCwgd2Ugd2lsbCBuZWVkIGl0IGZvciBsZWdhY3kKICAgICAgKiBzaXppbmcg b2YgQUNQSSB0YWJsZXMuCi0tIAoyLjE5LjEKCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fXwpYZW4tZGV2ZWwgbWFpbGluZyBsaXN0Clhlbi1kZXZlbEBsaXN0 cy54ZW5wcm9qZWN0Lm9yZwpodHRwczovL2xpc3RzLnhlbnByb2plY3Qub3JnL21haWxtYW4vbGlz dGluZm8veGVuLWRldmVs From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47096) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gJTup-0007xB-2t for qemu-devel@nongnu.org; Sun, 04 Nov 2018 20:42:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gJTun-00033h-4n for qemu-devel@nongnu.org; Sun, 04 Nov 2018 20:42:54 -0500 From: Samuel Ortiz Date: Mon, 5 Nov 2018 02:40:34 +0100 Message-Id: <20181105014047.26447-12-sameo@linux.intel.com> In-Reply-To: <20181105014047.26447-1-sameo@linux.intel.com> References: <20181105014047.26447-1-sameo@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v5 11/24] hw: acpi: Export and generalize the PCI host AML API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Shannon Zhao , Stefano Stabellini , Anthony Perard , Richard Henderson , Marcel Apfelbaum , xen-devel@lists.xenproject.org, Paolo Bonzini , "Michael S. Tsirkin" , Igor Mammedov , qemu-arm@nongnu.org, Peter Maydell , Eduardo Habkost , Yang Zhong , Rob Bradford From: Yang Zhong The AML build routines for the PCI host bridge and the corresponding DSDT addition are neither x86 nor PC machine type specific. We can move them to the architecture agnostic hw/acpi folder, and by carrying all the needed information through a new AcpiPciBus structure, we can make them PC machine type independent. Signed-off-by: Yang Zhong Signed-off-by: Rob Bradford Signed-off-by: Samuel Ortiz --- include/hw/acpi/aml-build.h | 8 ++ hw/acpi/aml-build.c | 157 ++++++++++++++++++++++++++++++++++++ hw/i386/acpi-build.c | 115 ++------------------------ 3 files changed, 173 insertions(+), 107 deletions(-) diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index fde2785b9a..1861e37ebf 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -229,6 +229,12 @@ typedef struct AcpiMcfgInfo { uint32_t mcfg_size; } AcpiMcfgInfo; +typedef struct AcpiPciBus { + PCIBus *pci_bus; + Range *pci_hole; + Range *pci_hole64; +} AcpiPciBus; + typedef struct CrsRangeEntry { uint64_t base; uint64_t limit; @@ -411,6 +417,8 @@ Aml *build_osc_method(uint32_t value); void build_mcfg(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info); Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi); Aml *build_prt(bool is_pci0_prt); +void acpi_dsdt_add_pci_bus(Aml *dsdt, AcpiPciBus *pci_host); +Aml *build_pci_host_bridge(Aml *table, AcpiPciBus *pci_host); void crs_range_set_init(CrsRangeSet *range_set); Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set); void crs_replace_with_free_ranges(GPtrArray *ranges, diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index b8e32f15f7..869ed70db3 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -29,6 +29,19 @@ #include "hw/pci/pci_bus.h" #include "qemu/range.h" #include "hw/pci/pci_bridge.h" +#include "hw/i386/pc.h" +#include "sysemu/tpm.h" +#include "hw/acpi/tpm.h" + +#define PCI_HOST_BRIDGE_CONFIG_ADDR 0xcf8 +#define PCI_HOST_BRIDGE_IO_0_MIN_ADDR 0x0000 +#define PCI_HOST_BRIDGE_IO_0_MAX_ADDR 0x0cf7 +#define PCI_HOST_BRIDGE_IO_1_MIN_ADDR 0x0d00 +#define PCI_HOST_BRIDGE_IO_1_MAX_ADDR 0xffff +#define PCI_VGA_MEM_BASE_ADDR 0x000a0000 +#define PCI_VGA_MEM_MAX_ADDR 0x000bffff +#define IO_0_LEN 0xcf8 +#define VGA_MEM_LEN 0x20000 static GArray *build_alloc_array(void) { @@ -2142,6 +2155,150 @@ Aml *build_prt(bool is_pci0_prt) return method; } +Aml *build_pci_host_bridge(Aml *table, AcpiPciBus *pci_host) +{ + CrsRangeEntry *entry; + Aml *scope, *dev, *crs; + CrsRangeSet crs_range_set; + Range *pci_hole = NULL; + Range *pci_hole64 = NULL; + PCIBus *bus = NULL; + int root_bus_limit = 0xFF; + int i; + + bus = pci_host->pci_bus; + assert(bus); + pci_hole = pci_host->pci_hole; + pci_hole64 = pci_host->pci_hole64; + + crs_range_set_init(&crs_range_set); + QLIST_FOREACH(bus, &bus->child, sibling) { + uint8_t bus_num = pci_bus_num(bus); + uint8_t numa_node = pci_bus_numa_node(bus); + + /* look only for expander root buses */ + if (!pci_bus_is_root(bus)) { + continue; + } + + if (bus_num < root_bus_limit) { + root_bus_limit = bus_num - 1; + } + + scope = aml_scope("\\_SB"); + dev = aml_device("PC%.02X", bus_num); + aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); + aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); + if (pci_bus_is_express(bus)) { + aml_append(dev, aml_name_decl("SUPP", aml_int(0))); + aml_append(dev, aml_name_decl("CTRL", aml_int(0))); + aml_append(dev, build_osc_method(0x1F)); + } + if (numa_node != NUMA_NODE_UNASSIGNED) { + aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); + } + + aml_append(dev, build_prt(false)); + crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); + aml_append(dev, aml_name_decl("_CRS", crs)); + aml_append(scope, dev); + aml_append(table, scope); + } + scope = aml_scope("\\_SB.PCI0"); + /* build PCI0._CRS */ + crs = aml_resource_template(); + /* set the pcie bus num */ + aml_append(crs, + aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, + 0x0000, 0x0, root_bus_limit, + 0x0000, root_bus_limit + 1)); + aml_append(crs, aml_io(AML_DECODE16, PCI_HOST_BRIDGE_CONFIG_ADDR, + PCI_HOST_BRIDGE_CONFIG_ADDR, 0x01, 0x08)); + /* set the io region 0 in pci host bridge */ + aml_append(crs, + aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, + AML_POS_DECODE, AML_ENTIRE_RANGE, + 0x0000, PCI_HOST_BRIDGE_IO_0_MIN_ADDR, + PCI_HOST_BRIDGE_IO_0_MAX_ADDR, 0x0000, IO_0_LEN)); + + /* set the io region 1 in pci host bridge */ + crs_replace_with_free_ranges(crs_range_set.io_ranges, + PCI_HOST_BRIDGE_IO_1_MIN_ADDR, + PCI_HOST_BRIDGE_IO_1_MAX_ADDR); + for (i = 0; i < crs_range_set.io_ranges->len; i++) { + entry = g_ptr_array_index(crs_range_set.io_ranges, i); + aml_append(crs, + aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, + AML_POS_DECODE, AML_ENTIRE_RANGE, + 0x0000, entry->base, entry->limit, + 0x0000, entry->limit - entry->base + 1)); + } + + /* set the vga mem region(0) in pci host bridge */ + aml_append(crs, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_CACHEABLE, AML_READ_WRITE, + 0, PCI_VGA_MEM_BASE_ADDR, PCI_VGA_MEM_MAX_ADDR, + 0, VGA_MEM_LEN)); + + /* set the mem region 1 in pci host bridge */ + crs_replace_with_free_ranges(crs_range_set.mem_ranges, + range_lob(pci_hole), + range_upb(pci_hole)); + for (i = 0; i < crs_range_set.mem_ranges->len; i++) { + entry = g_ptr_array_index(crs_range_set.mem_ranges, i); + aml_append(crs, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, + 0, entry->base, entry->limit, + 0, entry->limit - entry->base + 1)); + } + + /* set the mem region 2 in pci host bridge */ + if (!range_is_empty(pci_hole64)) { + crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, + range_lob(pci_hole64), + range_upb(pci_hole64)); + for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { + entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); + aml_append(crs, + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, + AML_MAX_FIXED, + AML_CACHEABLE, AML_READ_WRITE, + 0, entry->base, entry->limit, + 0, entry->limit - entry->base + 1)); + } + } + + if (TPM_IS_TIS(tpm_find())) { + aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, + TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); + } + + aml_append(scope, aml_name_decl("_CRS", crs)); + crs_range_set_free(&crs_range_set); + return scope; +} + +void acpi_dsdt_add_pci_bus(Aml *dsdt, AcpiPciBus *pci_host) +{ + Aml *dev, *pci_scope; + + dev = aml_device("\\_SB.PCI0"); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); + aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); + aml_append(dev, aml_name_decl("_ADR", aml_int(0))); + aml_append(dev, aml_name_decl("_UID", aml_int(1))); + aml_append(dev, aml_name_decl("SUPP", aml_int(0))); + aml_append(dev, aml_name_decl("CTRL", aml_int(0))); + aml_append(dev, build_osc_method(0x1F)); + aml_append(dsdt, dev); + + pci_scope = build_pci_host_bridge(dsdt, pci_host); + aml_append(dsdt, pci_scope); +} + /* Build rsdt table */ void build_rsdt(GArray *table_data, BIOSLinker *linker, GArray *table_offsets, diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index a5f5f83500..14e2624d14 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1253,16 +1253,11 @@ static void build_piix4_pci_hotplug(Aml *table) static void build_dsdt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm, AcpiMiscInfo *misc, - Range *pci_hole, Range *pci_hole64, + AcpiPciBus *pci_host, MachineState *machine, AcpiConfiguration *acpi_conf) { - CrsRangeEntry *entry; Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; - CrsRangeSet crs_range_set; uint32_t nr_mem = machine->ram_slots; - int root_bus_limit = 0xFF; - PCIBus *bus = NULL; - int i; dsdt = init_aml_allocator(); @@ -1337,104 +1332,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, } aml_append(dsdt, scope); - crs_range_set_init(&crs_range_set); - bus = PC_MACHINE(machine)->bus; - if (bus) { - QLIST_FOREACH(bus, &bus->child, sibling) { - uint8_t bus_num = pci_bus_num(bus); - uint8_t numa_node = pci_bus_numa_node(bus); - - /* look only for expander root buses */ - if (!pci_bus_is_root(bus)) { - continue; - } - - if (bus_num < root_bus_limit) { - root_bus_limit = bus_num - 1; - } - - scope = aml_scope("\\_SB"); - dev = aml_device("PC%.02X", bus_num); - aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); - aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); - aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); - if (pci_bus_is_express(bus)) { - aml_append(dev, build_osc_method(ACPI_OSC_CTRL_PCI_ALL)); - } - - if (numa_node != NUMA_NODE_UNASSIGNED) { - aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); - } - - aml_append(dev, build_prt(false)); - crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); - aml_append(dev, aml_name_decl("_CRS", crs)); - aml_append(scope, dev); - aml_append(dsdt, scope); - } - } - - scope = aml_scope("\\_SB.PCI0"); - /* build PCI0._CRS */ - crs = aml_resource_template(); - aml_append(crs, - aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, - 0x0000, 0x0, root_bus_limit, - 0x0000, root_bus_limit + 1)); - aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); - - aml_append(crs, - aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, - AML_POS_DECODE, AML_ENTIRE_RANGE, - 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); - - crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); - for (i = 0; i < crs_range_set.io_ranges->len; i++) { - entry = g_ptr_array_index(crs_range_set.io_ranges, i); - aml_append(crs, - aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, - AML_POS_DECODE, AML_ENTIRE_RANGE, - 0x0000, entry->base, entry->limit, - 0x0000, entry->limit - entry->base + 1)); - } - - aml_append(crs, - aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, - AML_CACHEABLE, AML_READ_WRITE, - 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); - - crs_replace_with_free_ranges(crs_range_set.mem_ranges, - range_lob(pci_hole), - range_upb(pci_hole)); - for (i = 0; i < crs_range_set.mem_ranges->len; i++) { - entry = g_ptr_array_index(crs_range_set.mem_ranges, i); - aml_append(crs, - aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, - 0, entry->base, entry->limit, - 0, entry->limit - entry->base + 1)); - } - - if (!range_is_empty(pci_hole64)) { - crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, - range_lob(pci_hole64), - range_upb(pci_hole64)); - for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { - entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); - aml_append(crs, - aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, - AML_MAX_FIXED, - AML_CACHEABLE, AML_READ_WRITE, - 0, entry->base, entry->limit, - 0, entry->limit - entry->base + 1)); - } - } - - if (TPM_IS_TIS(tpm_find())) { - aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, - TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); - } - aml_append(scope, aml_name_decl("_CRS", crs)); + scope = build_pci_host_bridge(dsdt, pci_host); /* reserve GPE0 block resources */ dev = aml_device("GPE0"); @@ -1454,8 +1352,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(dev, aml_name_decl("_CRS", crs)); aml_append(scope, dev); - crs_range_set_free(&crs_range_set); - /* reserve PCIHP resources */ if (pm->pcihp_io_len) { dev = aml_device("PHPR"); @@ -2012,6 +1908,11 @@ void acpi_build(AcpiBuildTables *tables, 64 /* Ensure FACS is aligned */, false /* high memory */); + AcpiPciBus pci_host = { + .pci_bus = PC_MACHINE(machine)->bus, + .pci_hole = &pci_hole, + .pci_hole64 = &pci_hole64, + }; /* * FACS is pointed to by FADT. * We place it first since it's the only table that has alignment @@ -2023,7 +1924,7 @@ void acpi_build(AcpiBuildTables *tables, /* DSDT is pointed to by FADT */ dsdt = tables_blob->len; build_dsdt(tables_blob, tables->linker, &pm, &misc, - &pci_hole, &pci_hole64, machine, acpi_conf); + &pci_host, machine, acpi_conf); /* Count the size of the DSDT and SSDT, we will need it for legacy * sizing of ACPI tables. -- 2.19.1