diff for duplicates of <20181105065807.GA1286@andestech.com> diff --git a/a/1.txt b/N1/1.txt index ef0ac10..eb72637 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,6 +1,6 @@ On Fri, Nov 02, 2018 at 01:48:57AM +0800, Karsten Merker wrote: > On Wed, Oct 31, 2018 at 10:27:05AM -0700, Palmer Dabbelt wrote: -> > On Wed, 31 Oct 2018 04:16:10 PDT (-0700), anup at brainfault.org wrote: +> > On Wed, 31 Oct 2018 04:16:10 PDT (-0700), anup@brainfault.org wrote: > > > On Wed, Oct 31, 2018 at 4:06 PM Vincent Chen <vincentc@andestech.com> wrote: > > > > > > > > RISC-V permits each vendor to develop respective extension ISA based @@ -97,3 +97,8 @@ requirements that one kernel image is bootable everywhere. Regards, Vincent + +_______________________________________________ +linux-riscv mailing list +linux-riscv@lists.infradead.org +http://lists.infradead.org/mailman/listinfo/linux-riscv diff --git a/a/content_digest b/N1/content_digest index ed610f5..02406a2 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,15 +1,25 @@ "ref\0CAAhSdy0Y_jdc=2Lf8epof_+7HigCfhDxMNe8EF0fHfncqhs-zA@mail.gmail.com\0" "ref\0mhng-01f0ac6a-c2fd-41be-9d53-44d1c139d453@palmer-si-x1c4\0" "ref\020181101174857.du2zu4vnrhpu5asf@excalibur.cnev.de\0" - "From\0vincentc@andestech.com (Vincent Chen)\0" - "Subject\0[RFC 0/2] RISC-V: A proposal to add vendor-specific code\0" + "From\0Vincent Chen <vincentc@andestech.com>\0" + "Subject\0Re: [RFC 0/2] RISC-V: A proposal to add vendor-specific code\0" "Date\0Mon, 5 Nov 2018 14:58:07 +0800\0" - "To\0linux-riscv@lists.infradead.org\0" + "To\0<palmer@sifive.com>" + " <aou@eecs.berkeley.edu>\0" + "Cc\0zong@andestech.com" + arnd@arndb.de + alankao@andestech.com + greentime@andestech.com + linux-kernel@vger.kernel.org + vincentc@andestech.com + kito@andestech.com + linux-riscv@lists.infradead.org + " deanbo422@gmail.com\0" "\00:1\0" "b\0" "On Fri, Nov 02, 2018 at 01:48:57AM +0800, Karsten Merker wrote:\n" "> On Wed, Oct 31, 2018 at 10:27:05AM -0700, Palmer Dabbelt wrote:\n" - "> > On Wed, 31 Oct 2018 04:16:10 PDT (-0700), anup at brainfault.org wrote:\n" + "> > On Wed, 31 Oct 2018 04:16:10 PDT (-0700), anup@brainfault.org wrote:\n" "> > > On Wed, Oct 31, 2018 at 4:06 PM Vincent Chen <vincentc@andestech.com> wrote:\n" "> > > > \n" "> > > > RISC-V permits each vendor to develop respective extension ISA based\n" @@ -105,6 +115,11 @@ "requirements that one kernel image is bootable everywhere.\n" "\n" "Regards,\n" - Vincent + "Vincent\n" + "\n" + "_______________________________________________\n" + "linux-riscv mailing list\n" + "linux-riscv@lists.infradead.org\n" + http://lists.infradead.org/mailman/listinfo/linux-riscv -d720a33a570bbd67c6a45b452c0cfafc56065a75a337b010f8a9848d501858be +26f0c16aca3b1655be703efca0102078caa66fa9d4399e24127f140cc1658840
diff --git a/a/1.txt b/N2/1.txt index ef0ac10..612e3d8 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,6 +1,6 @@ On Fri, Nov 02, 2018 at 01:48:57AM +0800, Karsten Merker wrote: > On Wed, Oct 31, 2018 at 10:27:05AM -0700, Palmer Dabbelt wrote: -> > On Wed, 31 Oct 2018 04:16:10 PDT (-0700), anup at brainfault.org wrote: +> > On Wed, 31 Oct 2018 04:16:10 PDT (-0700), anup@brainfault.org wrote: > > > On Wed, Oct 31, 2018 at 4:06 PM Vincent Chen <vincentc@andestech.com> wrote: > > > > > > > > RISC-V permits each vendor to develop respective extension ISA based diff --git a/a/content_digest b/N2/content_digest index ed610f5..7f08b17 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,15 +1,25 @@ "ref\0CAAhSdy0Y_jdc=2Lf8epof_+7HigCfhDxMNe8EF0fHfncqhs-zA@mail.gmail.com\0" "ref\0mhng-01f0ac6a-c2fd-41be-9d53-44d1c139d453@palmer-si-x1c4\0" "ref\020181101174857.du2zu4vnrhpu5asf@excalibur.cnev.de\0" - "From\0vincentc@andestech.com (Vincent Chen)\0" - "Subject\0[RFC 0/2] RISC-V: A proposal to add vendor-specific code\0" + "From\0Vincent Chen <vincentc@andestech.com>\0" + "Subject\0Re: [RFC 0/2] RISC-V: A proposal to add vendor-specific code\0" "Date\0Mon, 5 Nov 2018 14:58:07 +0800\0" - "To\0linux-riscv@lists.infradead.org\0" + "To\0<palmer@sifive.com>" + " <aou@eecs.berkeley.edu>\0" + "Cc\0<arnd@arndb.de>" + <linux-riscv@lists.infradead.org> + <linux-kernel@vger.kernel.org> + <greentime@andestech.com> + <alankao@andestech.com> + <vincentc@andestech.com> + <zong@andestech.com> + <deanbo422@gmail.com> + " <kito@andestech.com>\0" "\00:1\0" "b\0" "On Fri, Nov 02, 2018 at 01:48:57AM +0800, Karsten Merker wrote:\n" "> On Wed, Oct 31, 2018 at 10:27:05AM -0700, Palmer Dabbelt wrote:\n" - "> > On Wed, 31 Oct 2018 04:16:10 PDT (-0700), anup at brainfault.org wrote:\n" + "> > On Wed, 31 Oct 2018 04:16:10 PDT (-0700), anup@brainfault.org wrote:\n" "> > > On Wed, Oct 31, 2018 at 4:06 PM Vincent Chen <vincentc@andestech.com> wrote:\n" "> > > > \n" "> > > > RISC-V permits each vendor to develop respective extension ISA based\n" @@ -107,4 +117,4 @@ "Regards,\n" Vincent -d720a33a570bbd67c6a45b452c0cfafc56065a75a337b010f8a9848d501858be +76c0f57b564cd021f27d1dca61d1aff1327372c2d0548e0885edcd5df0f57ed4
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