diff for duplicates of <20181105140933.GA24038@linux.intel.com> diff --git a/a/2.hdr b/N1/2.hdr index 318d5b2..d717420 100644 --- a/a/2.hdr +++ b/N1/2.hdr @@ -1,3 +1,2 @@ -Content-Type: text/x-diff; charset="us-ascii" -Content-Disposition: attachment; - filename="0001-x86-cpu-intel-clean-up-detect_sgx-flow.patch" +Content-Type: text/x-diff; charset=us-ascii +Content-Disposition: attachment; filename="0001-x86-cpu-intel-clean-up-detect_sgx-flow.patch" diff --git a/a/2.txt b/N1/2.txt index 8b13789..967ea96 100644 --- a/a/2.txt +++ b/N1/2.txt @@ -1 +1,65 @@ +From 3b863a7db00cefffc15df918a5132c35ea313c27 Mon Sep 17 00:00:00 2001 +From: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com> +Date: Mon, 5 Nov 2018 16:06:06 +0200 +Subject: [PATCH] x86/cpu/intel: clean up detect_sgx() flow +Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com> +--- + arch/x86/kernel/cpu/intel.c | 32 ++++++++++++++++++++------------ + 1 file changed, 20 insertions(+), 12 deletions(-) + +diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c +index bc52c52f7025..8a20a193d399 100644 +--- a/arch/x86/kernel/cpu/intel.c ++++ b/arch/x86/kernel/cpu/intel.c +@@ -598,28 +598,36 @@ static void detect_tme(struct cpuinfo_x86 *c) + + static void detect_sgx(struct cpuinfo_x86 *c) + { +- bool unsupported = false; + unsigned long long fc; + + rdmsrl(MSR_IA32_FEATURE_CONTROL, fc); + if (!(fc & FEATURE_CONTROL_LOCKED)) { + pr_err_once("sgx: IA32_FEATURE_CONTROL MSR is not locked\n"); +- unsupported = true; +- } else if (!(fc & FEATURE_CONTROL_SGX_ENABLE)) { ++ goto out_unsupported; ++ } ++ ++ if (!(fc & FEATURE_CONTROL_SGX_ENABLE)) { + pr_err_once("sgx: not enabled in IA32_FEATURE_CONTROL MSR\n"); +- unsupported = true; +- } else if (!cpu_has(c, X86_FEATURE_SGX1)) { ++ goto out_unsupported; ++ } ++ ++ if (!cpu_has(c, X86_FEATURE_SGX1)) { + pr_err_once("sgx: SGX1 instruction set not supported\n"); +- unsupported = true; ++ goto out_unsupported; + } + +- if (unsupported) { +- setup_clear_cpu_cap(X86_FEATURE_SGX); +- setup_clear_cpu_cap(X86_FEATURE_SGX1); +- setup_clear_cpu_cap(X86_FEATURE_SGX2); ++ if (!(fc & FEATURE_CONTROL_SGX_LE_WR)) { ++ pr_info_once("sgx: launch control MSRs are not writable\n"); ++ goto out_msrs_rdonly; + } +- if (unsupported || !(fc & FEATURE_CONTROL_SGX_LE_WR)) +- setup_clear_cpu_cap(X86_FEATURE_SGX_LC); ++ ++ return; ++out_unsupported: ++ setup_clear_cpu_cap(X86_FEATURE_SGX); ++ setup_clear_cpu_cap(X86_FEATURE_SGX1); ++ setup_clear_cpu_cap(X86_FEATURE_SGX2); ++out_msrs_rdonly: ++ setup_clear_cpu_cap(X86_FEATURE_SGX_LC); + } + + static void init_intel_energy_perf(struct cpuinfo_x86 *c) +-- +2.19.1 diff --git a/a/content_digest b/N1/content_digest index bf401ec..151d790 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -7,15 +7,15 @@ "To\0Andy Shevchenko <andy.shevchenko@gmail.com>\0" "Cc\0maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT) <x86@kernel.org>" Platform Driver <platform-driver-x86@vger.kernel.org> - <linux-sgx@vger.kernel.org> + linux-sgx@vger.kernel.org Dave Hansen <dave.hansen@intel.com> - <sean.j.christopherson@intel.com> - <nhorman@redhat.com> - <npmccallum@redhat.com> - <serge.ayoun@intel.com> - <shay.katz-zamir@intel.com> - <haitao.huang@intel.com> - <mark.shanahan@intel.com> + sean.j.christopherson@intel.com + nhorman@redhat.com + npmccallum@redhat.com + serge.ayoun@intel.com + shay.katz-zamir@intel.com + haitao.huang@intel.com + mark.shanahan@intel.com Andy Shevchenko <andriy.shevchenko@linux.intel.com> Thomas Gleixner <tglx@linutronix.de> Ingo Molnar <mingo@redhat.com> @@ -23,11 +23,11 @@ H. Peter Anvin <hpa@zytor.com> Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> David Woodhouse <dwmw@amazon.co.uk> - <davidwang@zhaoxin.com> + davidwang@zhaoxin.com Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Levin Alexander (Sasha Levin) <alexander.levin@verizon.com> - <qianyue.zj@alibaba-inc.com> + qianyue.zj@alibaba-inc.com " Linux Kernel Mailing List <linux-kernel@vger.kernel.org>\0" "\01:1\0" "b\0" @@ -62,5 +62,70 @@ "\01:2\0" "fn\00001-x86-cpu-intel-clean-up-detect_sgx-flow.patch\0" "b\0" + "From 3b863a7db00cefffc15df918a5132c35ea313c27 Mon Sep 17 00:00:00 2001\n" + "From: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>\n" + "Date: Mon, 5 Nov 2018 16:06:06 +0200\n" + "Subject: [PATCH] x86/cpu/intel: clean up detect_sgx() flow\n" + "\n" + "Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>\n" + "---\n" + " arch/x86/kernel/cpu/intel.c | 32 ++++++++++++++++++++------------\n" + " 1 file changed, 20 insertions(+), 12 deletions(-)\n" + "\n" + "diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c\n" + "index bc52c52f7025..8a20a193d399 100644\n" + "--- a/arch/x86/kernel/cpu/intel.c\n" + "+++ b/arch/x86/kernel/cpu/intel.c\n" + "@@ -598,28 +598,36 @@ static void detect_tme(struct cpuinfo_x86 *c)\n" + " \n" + " static void detect_sgx(struct cpuinfo_x86 *c)\n" + " {\n" + "-\tbool unsupported = false;\n" + " \tunsigned long long fc;\n" + " \n" + " \trdmsrl(MSR_IA32_FEATURE_CONTROL, fc);\n" + " \tif (!(fc & FEATURE_CONTROL_LOCKED)) {\n" + " \t\tpr_err_once(\"sgx: IA32_FEATURE_CONTROL MSR is not locked\\n\");\n" + "-\t\tunsupported = true;\n" + "-\t} else if (!(fc & FEATURE_CONTROL_SGX_ENABLE)) {\n" + "+\t\tgoto out_unsupported;\n" + "+\t}\n" + "+\n" + "+\tif (!(fc & FEATURE_CONTROL_SGX_ENABLE)) {\n" + " \t\tpr_err_once(\"sgx: not enabled in IA32_FEATURE_CONTROL MSR\\n\");\n" + "-\t\tunsupported = true;\n" + "-\t} else if (!cpu_has(c, X86_FEATURE_SGX1)) {\n" + "+\t\tgoto out_unsupported;\n" + "+\t}\n" + "+\n" + "+\tif (!cpu_has(c, X86_FEATURE_SGX1)) {\n" + " \t\tpr_err_once(\"sgx: SGX1 instruction set not supported\\n\");\n" + "-\t\tunsupported = true;\n" + "+\t\tgoto out_unsupported;\n" + " \t}\n" + " \n" + "-\tif (unsupported) {\n" + "-\t\tsetup_clear_cpu_cap(X86_FEATURE_SGX);\n" + "-\t\tsetup_clear_cpu_cap(X86_FEATURE_SGX1);\n" + "-\t\tsetup_clear_cpu_cap(X86_FEATURE_SGX2);\n" + "+\tif (!(fc & FEATURE_CONTROL_SGX_LE_WR)) {\n" + "+\t\tpr_info_once(\"sgx: launch control MSRs are not writable\\n\");\n" + "+\t\tgoto out_msrs_rdonly;\n" + " \t}\n" + "-\tif (unsupported || !(fc & FEATURE_CONTROL_SGX_LE_WR))\n" + "-\t\tsetup_clear_cpu_cap(X86_FEATURE_SGX_LC);\n" + "+\n" + "+\treturn;\n" + "+out_unsupported:\n" + "+\tsetup_clear_cpu_cap(X86_FEATURE_SGX);\n" + "+\tsetup_clear_cpu_cap(X86_FEATURE_SGX1);\n" + "+\tsetup_clear_cpu_cap(X86_FEATURE_SGX2);\n" + "+out_msrs_rdonly:\n" + "+\tsetup_clear_cpu_cap(X86_FEATURE_SGX_LC);\n" + " }\n" + " \n" + " static void init_intel_energy_perf(struct cpuinfo_x86 *c)\n" + "-- \n" + 2.19.1 -c356fc1adf748cfb18dba62a700fec1c7a0a34536670fdddabdc13f548b3310b +e7a00cf306ac690edc4b066601d0d01db957d64f98e5eadc422767f785dd845e
diff --git a/a/2.hdr b/N2/2.hdr index 318d5b2..d717420 100644 --- a/a/2.hdr +++ b/N2/2.hdr @@ -1,3 +1,2 @@ -Content-Type: text/x-diff; charset="us-ascii" -Content-Disposition: attachment; - filename="0001-x86-cpu-intel-clean-up-detect_sgx-flow.patch" +Content-Type: text/x-diff; charset=us-ascii +Content-Disposition: attachment; filename="0001-x86-cpu-intel-clean-up-detect_sgx-flow.patch" diff --git a/a/2.txt b/N2/2.txt index 8b13789..967ea96 100644 --- a/a/2.txt +++ b/N2/2.txt @@ -1 +1,65 @@ +From 3b863a7db00cefffc15df918a5132c35ea313c27 Mon Sep 17 00:00:00 2001 +From: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com> +Date: Mon, 5 Nov 2018 16:06:06 +0200 +Subject: [PATCH] x86/cpu/intel: clean up detect_sgx() flow +Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com> +--- + arch/x86/kernel/cpu/intel.c | 32 ++++++++++++++++++++------------ + 1 file changed, 20 insertions(+), 12 deletions(-) + +diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c +index bc52c52f7025..8a20a193d399 100644 +--- a/arch/x86/kernel/cpu/intel.c ++++ b/arch/x86/kernel/cpu/intel.c +@@ -598,28 +598,36 @@ static void detect_tme(struct cpuinfo_x86 *c) + + static void detect_sgx(struct cpuinfo_x86 *c) + { +- bool unsupported = false; + unsigned long long fc; + + rdmsrl(MSR_IA32_FEATURE_CONTROL, fc); + if (!(fc & FEATURE_CONTROL_LOCKED)) { + pr_err_once("sgx: IA32_FEATURE_CONTROL MSR is not locked\n"); +- unsupported = true; +- } else if (!(fc & FEATURE_CONTROL_SGX_ENABLE)) { ++ goto out_unsupported; ++ } ++ ++ if (!(fc & FEATURE_CONTROL_SGX_ENABLE)) { + pr_err_once("sgx: not enabled in IA32_FEATURE_CONTROL MSR\n"); +- unsupported = true; +- } else if (!cpu_has(c, X86_FEATURE_SGX1)) { ++ goto out_unsupported; ++ } ++ ++ if (!cpu_has(c, X86_FEATURE_SGX1)) { + pr_err_once("sgx: SGX1 instruction set not supported\n"); +- unsupported = true; ++ goto out_unsupported; + } + +- if (unsupported) { +- setup_clear_cpu_cap(X86_FEATURE_SGX); +- setup_clear_cpu_cap(X86_FEATURE_SGX1); +- setup_clear_cpu_cap(X86_FEATURE_SGX2); ++ if (!(fc & FEATURE_CONTROL_SGX_LE_WR)) { ++ pr_info_once("sgx: launch control MSRs are not writable\n"); ++ goto out_msrs_rdonly; + } +- if (unsupported || !(fc & FEATURE_CONTROL_SGX_LE_WR)) +- setup_clear_cpu_cap(X86_FEATURE_SGX_LC); ++ ++ return; ++out_unsupported: ++ setup_clear_cpu_cap(X86_FEATURE_SGX); ++ setup_clear_cpu_cap(X86_FEATURE_SGX1); ++ setup_clear_cpu_cap(X86_FEATURE_SGX2); ++out_msrs_rdonly: ++ setup_clear_cpu_cap(X86_FEATURE_SGX_LC); + } + + static void init_intel_energy_perf(struct cpuinfo_x86 *c) +-- +2.19.1 diff --git a/a/content_digest b/N2/content_digest index bf401ec..28de2a5 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -7,15 +7,15 @@ "To\0Andy Shevchenko <andy.shevchenko@gmail.com>\0" "Cc\0maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT) <x86@kernel.org>" Platform Driver <platform-driver-x86@vger.kernel.org> - <linux-sgx@vger.kernel.org> + linux-sgx@vger.kernel.org Dave Hansen <dave.hansen@intel.com> - <sean.j.christopherson@intel.com> - <nhorman@redhat.com> - <npmccallum@redhat.com> - <serge.ayoun@intel.com> - <shay.katz-zamir@intel.com> - <haitao.huang@intel.com> - <mark.shanahan@intel.com> + sean.j.christopherson@intel.com + nhorman@redhat.com + npmccallum@redhat.com + serge.ayoun@intel.com + shay.katz-zamir@intel.com + haitao.huang@intel.com + mark.shanahan@intel.com Andy Shevchenko <andriy.shevchenko@linux.intel.com> Thomas Gleixner <tglx@linutronix.de> Ingo Molnar <mingo@redhat.com> @@ -23,12 +23,10 @@ H. Peter Anvin <hpa@zytor.com> Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> David Woodhouse <dwmw@amazon.co.uk> - <davidwang@zhaoxin.com> + davidwang@zhaoxin.com Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Levin - Alexander (Sasha Levin) <alexander.levin@verizon.com> - <qianyue.zj@alibaba-inc.com> - " Linux Kernel Mailing List <linux-kernel@vger.kernel.org>\0" + " Alexander (Sasha Levin) <alexander.levin@verizon.com>\0" "\01:1\0" "b\0" "On Sat, Nov 03, 2018 at 03:05:39PM +0200, Andy Shevchenko wrote:\n" @@ -62,5 +60,70 @@ "\01:2\0" "fn\00001-x86-cpu-intel-clean-up-detect_sgx-flow.patch\0" "b\0" + "From 3b863a7db00cefffc15df918a5132c35ea313c27 Mon Sep 17 00:00:00 2001\n" + "From: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>\n" + "Date: Mon, 5 Nov 2018 16:06:06 +0200\n" + "Subject: [PATCH] x86/cpu/intel: clean up detect_sgx() flow\n" + "\n" + "Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>\n" + "---\n" + " arch/x86/kernel/cpu/intel.c | 32 ++++++++++++++++++++------------\n" + " 1 file changed, 20 insertions(+), 12 deletions(-)\n" + "\n" + "diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c\n" + "index bc52c52f7025..8a20a193d399 100644\n" + "--- a/arch/x86/kernel/cpu/intel.c\n" + "+++ b/arch/x86/kernel/cpu/intel.c\n" + "@@ -598,28 +598,36 @@ static void detect_tme(struct cpuinfo_x86 *c)\n" + " \n" + " static void detect_sgx(struct cpuinfo_x86 *c)\n" + " {\n" + "-\tbool unsupported = false;\n" + " \tunsigned long long fc;\n" + " \n" + " \trdmsrl(MSR_IA32_FEATURE_CONTROL, fc);\n" + " \tif (!(fc & FEATURE_CONTROL_LOCKED)) {\n" + " \t\tpr_err_once(\"sgx: IA32_FEATURE_CONTROL MSR is not locked\\n\");\n" + "-\t\tunsupported = true;\n" + "-\t} else if (!(fc & FEATURE_CONTROL_SGX_ENABLE)) {\n" + "+\t\tgoto out_unsupported;\n" + "+\t}\n" + "+\n" + "+\tif (!(fc & FEATURE_CONTROL_SGX_ENABLE)) {\n" + " \t\tpr_err_once(\"sgx: not enabled in IA32_FEATURE_CONTROL MSR\\n\");\n" + "-\t\tunsupported = true;\n" + "-\t} else if (!cpu_has(c, X86_FEATURE_SGX1)) {\n" + "+\t\tgoto out_unsupported;\n" + "+\t}\n" + "+\n" + "+\tif (!cpu_has(c, X86_FEATURE_SGX1)) {\n" + " \t\tpr_err_once(\"sgx: SGX1 instruction set not supported\\n\");\n" + "-\t\tunsupported = true;\n" + "+\t\tgoto out_unsupported;\n" + " \t}\n" + " \n" + "-\tif (unsupported) {\n" + "-\t\tsetup_clear_cpu_cap(X86_FEATURE_SGX);\n" + "-\t\tsetup_clear_cpu_cap(X86_FEATURE_SGX1);\n" + "-\t\tsetup_clear_cpu_cap(X86_FEATURE_SGX2);\n" + "+\tif (!(fc & FEATURE_CONTROL_SGX_LE_WR)) {\n" + "+\t\tpr_info_once(\"sgx: launch control MSRs are not writable\\n\");\n" + "+\t\tgoto out_msrs_rdonly;\n" + " \t}\n" + "-\tif (unsupported || !(fc & FEATURE_CONTROL_SGX_LE_WR))\n" + "-\t\tsetup_clear_cpu_cap(X86_FEATURE_SGX_LC);\n" + "+\n" + "+\treturn;\n" + "+out_unsupported:\n" + "+\tsetup_clear_cpu_cap(X86_FEATURE_SGX);\n" + "+\tsetup_clear_cpu_cap(X86_FEATURE_SGX1);\n" + "+\tsetup_clear_cpu_cap(X86_FEATURE_SGX2);\n" + "+out_msrs_rdonly:\n" + "+\tsetup_clear_cpu_cap(X86_FEATURE_SGX_LC);\n" + " }\n" + " \n" + " static void init_intel_energy_perf(struct cpuinfo_x86 *c)\n" + "-- \n" + 2.19.1 -c356fc1adf748cfb18dba62a700fec1c7a0a34536670fdddabdc13f548b3310b +942f2dc12ebacb74b701c6c07571350dda58f593e35c507f78f363b169c7f11d
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