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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id t77-v6sm7621832lfi.63.2018.11.05.07.23.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Nov 2018 07:23:17 -0800 (PST) Date: Mon, 5 Nov 2018 16:23:00 +0100 From: "Edgar E. Iglesias" To: Peter Maydell Message-ID: <20181105152300.GA1148@toto> References: <20181016093703.10637-1-peter.maydell@linaro.org> <20181016093703.10637-2-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20181016093703.10637-2-peter.maydell@linaro.org> User-Agent: Mutt/1.9.4 (2018-02-28) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::144 Subject: Re: [Qemu-arm] [PATCH 1/2] target/arm: Set S and PTW in 64-bit PAR format X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: fIhfzlG0IVZN On Tue, Oct 16, 2018 at 10:37:02AM +0100, Peter Maydell wrote: > In do_ats_write() we construct a PAR value based on the result > of the translation. A comment says "S2WLK and FSTAGE are always > zero, because we don't implement virtualization". > Since we do in fact now implement virtualization, add the missing > code that sets these bits based on the reported ARMMMUFaultInfo. > > (These bits are named PTW and S in ARMv8, so we follow that > convention in the new comments in this patch.) > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target/arm/helper.c | 10 ++++++---- > 1 file changed, 6 insertions(+), 4 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 43afdd082e1..dc849b09893 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -2344,10 +2344,12 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, > > par64 |= 1; /* F */ > par64 |= (fsr & 0x3f) << 1; /* FS */ > - /* Note that S2WLK and FSTAGE are always zero, because we don't > - * implement virtualization and therefore there can't be a stage 2 > - * fault. > - */ > + if (fi.stage2) { > + par64 |= (1 << 9); /* S */ > + } > + if (fi.s1ptw) { > + par64 |= (1 << 8); /* PTW */ > + } > } > } else { > /* fsr is a DFSR/IFSR value for the short descriptor > -- > 2.19.0 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52196) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gJgjJ-0007RW-D4 for qemu-devel@nongnu.org; Mon, 05 Nov 2018 10:23:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gJgjH-0004ET-1l for qemu-devel@nongnu.org; Mon, 05 Nov 2018 10:23:53 -0500 Date: Mon, 5 Nov 2018 16:23:00 +0100 From: "Edgar E. Iglesias" Message-ID: <20181105152300.GA1148@toto> References: <20181016093703.10637-1-peter.maydell@linaro.org> <20181016093703.10637-2-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20181016093703.10637-2-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH 1/2] target/arm: Set S and PTW in 64-bit PAR format List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org On Tue, Oct 16, 2018 at 10:37:02AM +0100, Peter Maydell wrote: > In do_ats_write() we construct a PAR value based on the result > of the translation. A comment says "S2WLK and FSTAGE are always > zero, because we don't implement virtualization". > Since we do in fact now implement virtualization, add the missing > code that sets these bits based on the reported ARMMMUFaultInfo. > > (These bits are named PTW and S in ARMv8, so we follow that > convention in the new comments in this patch.) > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target/arm/helper.c | 10 ++++++---- > 1 file changed, 6 insertions(+), 4 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 43afdd082e1..dc849b09893 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -2344,10 +2344,12 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, > > par64 |= 1; /* F */ > par64 |= (fsr & 0x3f) << 1; /* FS */ > - /* Note that S2WLK and FSTAGE are always zero, because we don't > - * implement virtualization and therefore there can't be a stage 2 > - * fault. > - */ > + if (fi.stage2) { > + par64 |= (1 << 9); /* S */ > + } > + if (fi.s1ptw) { > + par64 |= (1 << 8); /* PTW */ > + } > } > } else { > /* fsr is a DFSR/IFSR value for the short descriptor > -- > 2.19.0 > >