From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v1,1/2] dt-bindings: dmaengine: dw-dmac: add protection control property From: Rob Herring Message-Id: <20181105230652.GA22828@bogus> Date: Mon, 5 Nov 2018 17:06:52 -0600 To: Christian Lamparter Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, Dan Williams , Vinod Koul , Andy Shevchenko , Viresh Kumar , Mark Rutland List-ID: T24gU3VuLCBOb3YgMDQsIDIwMTggYXQgMDY6MDE6MzhQTSArMDEwMCwgQ2hyaXN0aWFuIExhbXBh cnRlciB3cm90ZToKPiBUaGlzIHBhdGNoIGFkZHMgdGhlIHBlci1jaGFubmVsIGRtYSBwcm90ZWN0 aW9uIGNvbnRyb2wKPiBwcm9wLWVuY29kZWQtYXJyYXkgYW5kIGR0LWJpbmRpbmcgZGVmaW5pdGlv bnMgKGluY2x1ZGluZwo+IGRlZmluaXRpb25zIGZvciB0aGUgZXhpc3RpbmcgY2hhbm5lbCBhbGxv Y2F0aW9uIGFuZCBwcmlvcml0eQo+IG9yZGVyIHZhbHVlcyBiYXNlZCBvbiBpbmNsdWRlL2xpbnV4 L3BsYXRmb3JtX2RhdGEvZG1hLWR3LmgpCj4gZm9yIHRoZSBEZXNpZ25XYXJlIEFIQiBDZW50cmFs IERpcmVjdCBNZW1vcnkgQWNjZXNzIENvbnRyb2xsZXIuCj4gCj4gTm90ZTogVGhlIHByb3RlY3Rp b24gY29udHJvbCBzaWduYWxzIGFyZSBvbmUtdG8tb25lIG1hcHBlZCB0bwo+IHRoZSBBSEIgSFBS T1RbMTozXSBzaWduYWxzLiAgVGhlIEhQUk9UMCAoRGF0YSBBY2Nlc3MpIGlzCj4gYWx3YXlzIGhh cmR3aXJlZCB0byAxIGZvciB0aGlzIGNvbnRyb2xsZXIuCj4gCj4gU2lnbmVkLW9mZi1ieTogQ2hy aXN0aWFuIExhbXBhcnRlciA8Y2h1bmtlZXlAZ21haWwuY29tPgo+IC0tLQo+ICAuLi4vZGV2aWNl dHJlZS9iaW5kaW5ncy9kbWEvc25wcy1kbWEudHh0ICAgICAgfCAgNCArKysrCj4gIE1BSU5UQUlO RVJTICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICB8ICA0ICsrKy0KPiAgaW5jbHVk ZS9kdC1iaW5kaW5ncy9kbWEvZHctZG1hYy5oICAgICAgICAgICAgIHwgMjAgKysrKysrKysrKysr KysrKysrKwo+ICAzIGZpbGVzIGNoYW5nZWQsIDI3IGluc2VydGlvbnMoKyksIDEgZGVsZXRpb24o LSkKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGluY2x1ZGUvZHQtYmluZGluZ3MvZG1hL2R3LWRtYWMu aAo+IAo+IGRpZmYgLS1naXQgYS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZG1h L3NucHMtZG1hLnR4dCBiL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9kbWEvc25w cy1kbWEudHh0Cj4gaW5kZXggMzllMmIyNmJlMzQ0Li43MmI0OTg0YTRjMTggMTAwNjQ0Cj4gLS0t IGEvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL2RtYS9zbnBzLWRtYS50eHQKPiAr KysgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZG1hL3NucHMtZG1hLnR4dAo+ IEBAIC0yNyw2ICsyNywxMCBAQCBPcHRpb25hbCBwcm9wZXJ0aWVzOgo+ICAgIGdlbmVyYWwgcHVy cG9zZSBETUEgY2hhbm5lbCBhbGxvY2F0b3IuIEZhbHNlIGlmIG5vdCBwYXNzZWQuCj4gIC0gbXVs dGktYmxvY2s6IE11bHRpIGJsb2NrIHRyYW5zZmVycyBzdXBwb3J0ZWQgYnkgaGFyZHdhcmUuIEFy cmF5IHByb3BlcnR5IHdpdGgKPiAgICBvbmUgY2VsbCBwZXIgY2hhbm5lbC4gMDogbm90IHN1cHBv cnRlZCwgMSAoZGVmYXVsdCk6IHN1cHBvcnRlZC4KPiArLSBzbnBzLGRtYS1wcm90ZWN0aW9uLWNv bnRyb2w6IENoYW5uZWwncyBBSEIgSFBST1RbMzoxXSBwcm90ZWN0aW9uIHNldHRpbmcuCj4gKyAg QXJyYXkgcHJvcGVydHkgd2l0aCBvbmUgY2VsbCBwZXIgY2hhbm5lbC4gVGhlIGRlZmF1bHQgdmFs dWUgZm9yIGEgY2hhbm5lbAo+ICsgIGlzIDAgKGZvciBub24tY2FjaGVhYmxlLCBzdHJvbmdseSBv cmRlcmVkLCB1bnByaXZpbGVnZWQgZGF0YSBhY2Nlc3MpLgoKSUlSQywgJ3N0cm9uZ2x5IG9yZGVy ZWQnIGlzIG91dHNpZGUgdGhlIHNjb3BlIG9mIEFIQiAoYW5kIEFYSSkgCmRlZmluaXRpb25zLiBU aGVyZSBpcyBhIG1hcHBpbmcgb2YgU08gcGFnZSB0YWJsZSBlbnRyaWVzIHRvIGJ1cyBjb250cm9s IApzaWduYWxzLCBidXQgdGhhdCdzIHBhcnQgb2YgdGhlIGNwdSBhbmQgb3V0c2lkZSB0aGUgc2Nv cGUgb2YgdGhpcyBkb2MuCgo+ICsgIFJlZmVyIHRvIGluY2x1ZGUvZHQtYmluZGluZ3MvZG1hL2R3 LWRtYWMuaCBmb3IgcG9zc2libGUgdmFsdWVzLgoKRG8geW91IHJlYWxseSBuZWVkIHRoaXMgdG8g YmUgcGVyIGNoYW5uZWwgcmF0aGVyIHRoYW4ganVzdCBwZXIgcGxhdGZvcm0/IApJZiBhbnl0aGlu ZywgdGhlIG9wdGltYWwgc2V0dGluZyBpcyBwcm9iYWJseSBiYXNlZCBvbiB0aGUgbWVtb3J5IGFk ZHJlc3MgCihkZXZpY2UsIG9uLWNoaXAgUkFNLCBvciBEUkFNKSwgbm90IHRoZSBjaGFubmVsLiAK CkknZCBleHBlY3QgZm9yIG1vc3QgcGxhdGZvcm1zLCBidWZmZXJhYmxlIHdvcmtzIHdpdGhvdXQg YW55IHMvdyBpc3N1ZQooYW5kIHNob3VsZCBiZSBtb3JlIGNvcnJlY3QgaW4gdGhhdCBjb2hlcmVu dCBhbGxvY2F0aW9ucyBhcmUgYnVmZmVyYWJsZSAKKGF0IGxlYXN0IGZvciBBUk0pLiBDYWNoZWFi bGUgcHJvYmFibHkgaGFzIG5vIGVmZmVjdCBhcyBtb3N0IHN5c3RlbXMgCmRvbid0IGhhdmUgY29o ZXJlbnQgaS9vIChhZ2FpbiwgYXQgbGVhc3QgZm9yIEFSTSkuCgoKPiAgRXhhbXBsZToKPiAgCj4g ZGlmZiAtLWdpdCBhL01BSU5UQUlORVJTIGIvTUFJTlRBSU5FUlMKPiBpbmRleCBkYWNiYTIzYjgw YjQuLmMzNTk5OGUyMGU5ZCAxMDA2NDQKPiAtLS0gYS9NQUlOVEFJTkVSUwo+ICsrKyBiL01BSU5U QUlORVJTCj4gQEAgLTE0MTA3LDkgKzE0MTA3LDExIEBAIFNZTk9QU1lTIERFU0lHTldBUkUgRE1B QyBEUklWRVIKPiAgTToJVmlyZXNoIEt1bWFyIDx2aXJlc2hrQGtlcm5lbC5vcmc+Cj4gIFI6CUFu ZHkgU2hldmNoZW5rbyA8YW5kcml5LnNoZXZjaGVua29AbGludXguaW50ZWwuY29tPgo+ICBTOglN YWludGFpbmVkCj4gK0Y6CURvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9kbWEvc25w cy1kbWEudHh0Cj4gK0Y6CWRyaXZlcnMvZG1hL2R3Lwo+ICtGOglpbmNsdWRlL2R0LWJpbmRpbmdz L2RtYS9kdy1kbWFjLmgKPiAgRjoJaW5jbHVkZS9saW51eC9kbWEvZHcuaAo+ICBGOglpbmNsdWRl L2xpbnV4L3BsYXRmb3JtX2RhdGEvZG1hLWR3LmgKPiAtRjoJZHJpdmVycy9kbWEvZHcvCj4gIAo+ ICBTWU5PUFNZUyBERVNJR05XQVJFIEVOVEVSUFJJU0UgRVRIRVJORVQgRFJJVkVSCj4gIE06CUpv c2UgQWJyZXUgPEpvc2UuQWJyZXVAc3lub3BzeXMuY29tPgo+IGRpZmYgLS1naXQgYS9pbmNsdWRl L2R0LWJpbmRpbmdzL2RtYS9kdy1kbWFjLmggYi9pbmNsdWRlL2R0LWJpbmRpbmdzL2RtYS9kdy1k bWFjLmgKPiBuZXcgZmlsZSBtb2RlIDEwMDY0NAo+IGluZGV4IDAwMDAwMDAwMDAwMC4uOTE1MmE2 ZTI0MDZjCj4gLS0tIC9kZXYvbnVsbAo+ICsrKyBiL2luY2x1ZGUvZHQtYmluZGluZ3MvZG1hL2R3 LWRtYWMuaAo+IEBAIC0wLDAgKzEsMjAgQEAKPiArLyogU1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6 IChHUEwtMi4wIE9SIE1JVCkgKi8KPiArCj4gKyNpZm5kZWYgX19EVF9CSU5ESU5HU19ETUFfRFdf RE1BQ19IX18KPiArI2RlZmluZSBfX0RUX0JJTkRJTkdTX0RNQV9EV19ETUFDX0hfXwo+ICsKPiAr I2RlZmluZSBEV19ETUFDX0NIQU5fQUxMT0NBVElPTl9BU0NFTkRJTkcgICAgICAgMCAgICAgICAv KiB6ZXJvIHRvIHNldmVuICovCj4gKyNkZWZpbmUgRFdfRE1BQ19DSEFOX0FMTE9DQVRJT05fREVT Q0VORElORyAgICAgIDEgICAgICAgLyogc2V2ZW4gdG8gemVybyAqLwo+ICsjZGVmaW5lIERXX0RN QUNfQ0hBTl9QUklPUklUWV9BU0NFTkRJTkcgICAgICAgICAwICAgICAgIC8qIGNoYW4wIGhpZ2hl c3QgKi8KPiArI2RlZmluZSBEV19ETUFDX0NIQU5fUFJJT1JJVFlfREVTQ0VORElORyAgICAgICAg MSAgICAgICAvKiBjaGFuNyBoaWdoZXN0ICovCgpUaGVzZSBzZWVtIHVucmVsYXRlZD8KCj4gKwo+ ICsvKgo+ICsgKiBQcm90ZWN0aW9uIENvbnRyb2wgYml0cyBwcm92aWRlIHByb3RlY3Rpb24gYWdh aW5zdCBpbGxlZ2FsIHRyYW5zYWN0aW9ucy4KPiArICogVGhlIHByb3RlY3Rpb24gYml0c1swOjJd IGFyZSBvbmUtdG8tb25lIG1hcHBlZCB0byBBSEIgSFBST1RbMzoxXSBzaWduYWxzLgo+ICsgKiBU aGUgQUhCIEhQUk9UWzBdIGJpdCBpcyBoYXJkd2lyZWQgdG8gMTogRGF0YSBBY2Nlc3MuCj4gKyAq Lwo+ICsjZGVmaW5lIERXX0RNQUNfSFBST1QxX1BSSVZJTEVHRURfTU9ERQkoMSA8PCAwKQkvKiBQ cml2aWxlZ2VkIE1vZGUgKi8KPiArI2RlZmluZSBEV19ETUFDX0hQUk9UMl9CVUZGRVJBQkxFCSgx IDw8IDEpCS8qIERNQSBpcyBidWZmZXJhYmxlICovCj4gKyNkZWZpbmUgRFdfRE1BQ19IUFJPVDNf Q0FDSEVBQkxFCSgxIDw8IDIpCS8qIERNQSBpcyBjYWNoZWFibGUgKi8KPiArCj4gKyNlbmRpZiAv KiBfX0RUX0JJTkRJTkdTX0RNQV9EV19ETUFDX0hfXyAqLwo+IC0tIAo+IDIuMTkuMQo+Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Mon, 5 Nov 2018 17:06:52 -0600 From: Rob Herring Subject: Re: [PATCH v1 1/2] dt-bindings: dmaengine: dw-dmac: add protection control property Message-ID: <20181105230652.GA22828@bogus> References: <6b18bcf33d6473c166b607a5fa31ba63727cf6bb.1541350844.git.chunkeey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <6b18bcf33d6473c166b607a5fa31ba63727cf6bb.1541350844.git.chunkeey@gmail.com> To: Christian Lamparter Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, Dan Williams , Vinod Koul , Andy Shevchenko , Viresh Kumar , Mark Rutland List-ID: On Sun, Nov 04, 2018 at 06:01:38PM +0100, Christian Lamparter wrote: > This patch adds the per-channel dma protection control > prop-encoded-array and dt-binding definitions (including > definitions for the existing channel allocation and priority > order values based on include/linux/platform_data/dma-dw.h) > for the DesignWare AHB Central Direct Memory Access Controller. > > Note: The protection control signals are one-to-one mapped to > the AHB HPROT[1:3] signals. The HPROT0 (Data Access) is > always hardwired to 1 for this controller. > > Signed-off-by: Christian Lamparter > --- > .../devicetree/bindings/dma/snps-dma.txt | 4 ++++ > MAINTAINERS | 4 +++- > include/dt-bindings/dma/dw-dmac.h | 20 +++++++++++++++++++ > 3 files changed, 27 insertions(+), 1 deletion(-) > create mode 100644 include/dt-bindings/dma/dw-dmac.h > > diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt b/Documentation/devicetree/bindings/dma/snps-dma.txt > index 39e2b26be344..72b4984a4c18 100644 > --- a/Documentation/devicetree/bindings/dma/snps-dma.txt > +++ b/Documentation/devicetree/bindings/dma/snps-dma.txt > @@ -27,6 +27,10 @@ Optional properties: > general purpose DMA channel allocator. False if not passed. > - multi-block: Multi block transfers supported by hardware. Array property with > one cell per channel. 0: not supported, 1 (default): supported. > +- snps,dma-protection-control: Channel's AHB HPROT[3:1] protection setting. > + Array property with one cell per channel. The default value for a channel > + is 0 (for non-cacheable, strongly ordered, unprivileged data access). IIRC, 'strongly ordered' is outside the scope of AHB (and AXI) definitions. There is a mapping of SO page table entries to bus control signals, but that's part of the cpu and outside the scope of this doc. > + Refer to include/dt-bindings/dma/dw-dmac.h for possible values. Do you really need this to be per channel rather than just per platform? If anything, the optimal setting is probably based on the memory address (device, on-chip RAM, or DRAM), not the channel. I'd expect for most platforms, bufferable works without any s/w issue (and should be more correct in that coherent allocations are bufferable (at least for ARM). Cacheable probably has no effect as most systems don't have coherent i/o (again, at least for ARM). > Example: > > diff --git a/MAINTAINERS b/MAINTAINERS > index dacba23b80b4..c35998e20e9d 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -14107,9 +14107,11 @@ SYNOPSYS DESIGNWARE DMAC DRIVER > M: Viresh Kumar > R: Andy Shevchenko > S: Maintained > +F: Documentation/devicetree/bindings/dma/snps-dma.txt > +F: drivers/dma/dw/ > +F: include/dt-bindings/dma/dw-dmac.h > F: include/linux/dma/dw.h > F: include/linux/platform_data/dma-dw.h > -F: drivers/dma/dw/ > > SYNOPSYS DESIGNWARE ENTERPRISE ETHERNET DRIVER > M: Jose Abreu > diff --git a/include/dt-bindings/dma/dw-dmac.h b/include/dt-bindings/dma/dw-dmac.h > new file mode 100644 > index 000000000000..9152a6e2406c > --- /dev/null > +++ b/include/dt-bindings/dma/dw-dmac.h > @@ -0,0 +1,20 @@ > +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ > + > +#ifndef __DT_BINDINGS_DMA_DW_DMAC_H__ > +#define __DT_BINDINGS_DMA_DW_DMAC_H__ > + > +#define DW_DMAC_CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ > +#define DW_DMAC_CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ > +#define DW_DMAC_CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ > +#define DW_DMAC_CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ These seem unrelated? > + > +/* > + * Protection Control bits provide protection against illegal transactions. > + * The protection bits[0:2] are one-to-one mapped to AHB HPROT[3:1] signals. > + * The AHB HPROT[0] bit is hardwired to 1: Data Access. > + */ > +#define DW_DMAC_HPROT1_PRIVILEGED_MODE (1 << 0) /* Privileged Mode */ > +#define DW_DMAC_HPROT2_BUFFERABLE (1 << 1) /* DMA is bufferable */ > +#define DW_DMAC_HPROT3_CACHEABLE (1 << 2) /* DMA is cacheable */ > + > +#endif /* __DT_BINDINGS_DMA_DW_DMAC_H__ */ > -- > 2.19.1 >