From: Greg KH <gregkh@linuxfoundation.org>
To: Sai Praneeth Prakhya <sai.praneeth.prakhya@intel.com>
Cc: stable@vger.kernel.org, Thomas Gleixner <tglx@linutronix.de>,
Tim C Chen <tim.c.chen@intel.com>,
Dave Hansen <dave.hansen@intel.com>,
Ravi Shankar <ravi.v.shankar@intel.com>,
Andi Kleen <ak@linux.intel.com>
Subject: Re: [PATCH] x86/speculation: Support Enhanced IBRS on future CPUs
Date: Wed, 7 Nov 2018 10:26:08 +0100 [thread overview]
Message-ID: <20181107092608.GH31015@kroah.com> (raw)
In-Reply-To: <1541550365-95079-1-git-send-email-sai.praneeth.prakhya@intel.com>
On Tue, Nov 06, 2018 at 04:26:05PM -0800, Sai Praneeth Prakhya wrote:
> From: Sai Praneeth <sai.praneeth.prakhya@intel.com>
>
> [ Upstream commit 706d51681d636a0c4a5ef53395ec3b803e45ed4d ]
>
> Changes from upstream:
> ----------------------
> 1. Use bit 30 of word 7 in cpufeatures for X86_FEATURE_IBRS_ENHANCED as bit 29
> is now used by L1TF.
> 2. Fix some trivial line fuzzing.
>
> Note: Based on kernel version "Linux 4.18.17" and to be applied on both "Linux
> 4.18.17" and "Linux 4.14.79".
Ah, here's the other patch, please fix it up so I do not have to
hand-edit a file to apply this.
greg k-h
next prev parent reply other threads:[~2018-11-07 18:55 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-07 0:26 [PATCH] x86/speculation: Support Enhanced IBRS on future CPUs Sai Praneeth Prakhya
2018-11-07 9:26 ` Greg KH [this message]
-- strict thread matches above, loose matches on Subject: below --
2018-11-07 0:42 Sai Praneeth Prakhya
2018-11-07 9:25 ` Greg KH
2018-11-07 18:05 ` Prakhya, Sai Praneeth
2018-07-24 20:53 Sai Praneeth Prakhya
2018-07-30 12:25 ` Thomas Gleixner
2018-07-30 14:29 ` Dave Hansen
2018-07-30 16:58 ` Thomas Gleixner
2018-07-30 17:07 ` Prakhya, Sai Praneeth
2018-07-30 17:11 ` Thomas Gleixner
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