diff for duplicates of <20181116232524.GA2013@bogus> diff --git a/a/1.txt b/N1/1.txt index 24af4d7..66603ce 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -775,7 +775,7 @@ This is really 4 independent clocks or is 1 clock connected to 4 sinks? > + #address-cells = <1>; > + #size-cells = <0>; > + -> + A53_0: cpu at 0 { +> + A53_0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x0>; @@ -783,7 +783,7 @@ This is really 4 independent clocks or is 1 clock connected to 4 sinks? > + next-level-cache = <&A53_L2>; > + }; > + -> + A53_1: cpu at 1 { +> + A53_1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x1>; @@ -791,7 +791,7 @@ This is really 4 independent clocks or is 1 clock connected to 4 sinks? > + next-level-cache = <&A53_L2>; > + }; > + -> + A53_2: cpu at 2 { +> + A53_2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x2>; @@ -799,7 +799,7 @@ This is really 4 independent clocks or is 1 clock connected to 4 sinks? > + next-level-cache = <&A53_L2>; > + }; > + -> + A53_3: cpu at 3 { +> + A53_3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x3>; @@ -827,22 +827,22 @@ This is really 4 independent clocks or is 1 clock connected to 4 sinks? > + arm,no-tick-in-suspend; > + }; > + -> + peripherals at 0 { +> + peripherals@0 { -bus at 0 or soc at 0 +bus@0 or soc@0 > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x0 0x0 0x3e000000>; > + -> + bus at 30000000 { /* AIPS1 */ +> + bus@30000000 { /* AIPS1 */ > + compatible = "fsl,imx8mq-aips-bus", "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x30000000 0x30000000 0x400000>; > + -> + gpio1: gpio at 30200000 { +> + gpio1: gpio@30200000 { > + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; > + reg = <0x30200000 0x10000>; > + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, @@ -853,7 +853,7 @@ bus at 0 or soc at 0 > + #interrupt-cells = <2>; > + }; > + -> + gpio2: gpio at 30210000 { +> + gpio2: gpio@30210000 { > + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; > + reg = <0x30210000 0x10000>; > + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, @@ -864,7 +864,7 @@ bus at 0 or soc at 0 > + #interrupt-cells = <2>; > + }; > + -> + gpio3: gpio at 30220000 { +> + gpio3: gpio@30220000 { > + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; > + reg = <0x30220000 0x10000>; > + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, @@ -875,7 +875,7 @@ bus at 0 or soc at 0 > + #interrupt-cells = <2>; > + }; > + -> + gpio4: gpio at 30230000 { +> + gpio4: gpio@30230000 { > + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; > + reg = <0x30230000 0x10000>; > + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, @@ -886,7 +886,7 @@ bus at 0 or soc at 0 > + #interrupt-cells = <2>; > + }; > + -> + gpio5: gpio at 30240000 { +> + gpio5: gpio@30240000 { > + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; > + reg = <0x30240000 0x10000>; > + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, @@ -897,23 +897,23 @@ bus at 0 or soc at 0 > + #interrupt-cells = <2>; > + }; > + -> + iomuxc: iomuxc at 30330000 { +> + iomuxc: iomuxc@30330000 { > + compatible = "fsl,imx8mq-iomuxc"; > + reg = <0x30330000 0x10000>; > + }; > + -> + iomuxc_gpr: syscon at 30340000 { +> + iomuxc_gpr: syscon@30340000 { > + compatible = "fsl,imx8mq-iomuxc-gpr", "syscon"; > + reg = <0x30340000 0x10000>; > + }; > + -> + anatop: syscon at 30360000 { +> + anatop: syscon@30360000 { > + compatible = "fsl,imx8mq-anatop", "syscon"; > + reg = <0x30360000 0x10000>; > + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; > + }; > + -> + clk: clock-controller at 30380000 { +> + clk: clock-controller@30380000 { > + compatible = "fsl,imx8mq-ccm"; > + reg = <0x30380000 0x10000>; > + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, @@ -928,20 +928,20 @@ bus at 0 or soc at 0 > + }; > + }; > + -> + bus at 30400000 { /* AIPS2 */ +> + bus@30400000 { /* AIPS2 */ > + compatible = "fsl,imx8mq-aips-bus", "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x30400000 0x30400000 0x400000>; > + }; > + -> + bus at 30800000 { /* AIPS3 */ +> + bus@30800000 { /* AIPS3 */ > + compatible = "fsl,imx8mq-aips-bus", "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x30800000 0x30800000 0x400000>; > + -> + uart1: serial at 30860000 { +> + uart1: serial@30860000 { > + compatible = "fsl,imx8mq-uart", > + "fsl,imx6q-uart"; > + reg = <0x30860000 0x10000>; @@ -952,7 +952,7 @@ bus at 0 or soc at 0 > + status = "disabled"; > + }; > + -> + uart3: serial at 30880000 { +> + uart3: serial@30880000 { > + compatible = "fsl,imx8mq-uart", > + "fsl,imx6q-uart"; > + reg = <0x30880000 0x10000>; @@ -963,7 +963,7 @@ bus at 0 or soc at 0 > + status = "disabled"; > + }; > + -> + uart2: serial at 30890000 { +> + uart2: serial@30890000 { > + compatible = "fsl,imx8mq-uart", > + "fsl,imx6q-uart"; > + reg = <0x30890000 0x10000>; @@ -974,7 +974,7 @@ bus at 0 or soc at 0 > + status = "disabled"; > + }; > + -> + i2c1: i2c at 30a20000 { +> + i2c1: i2c@30a20000 { > + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; > + reg = <0x30a20000 0x10000>; > + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; @@ -984,7 +984,7 @@ bus at 0 or soc at 0 > + status = "disabled"; > + }; > + -> + i2c2: i2c at 30a30000 { +> + i2c2: i2c@30a30000 { > + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; > + reg = <0x30a30000 0x10000>; > + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; @@ -994,7 +994,7 @@ bus at 0 or soc at 0 > + status = "disabled"; > + }; > + -> + i2c3: i2c at 30a40000 { +> + i2c3: i2c@30a40000 { > + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; > + reg = <0x30a40000 0x10000>; > + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; @@ -1004,7 +1004,7 @@ bus at 0 or soc at 0 > + status = "disabled"; > + }; > + -> + i2c4: i2c at 30a50000 { +> + i2c4: i2c@30a50000 { > + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; > + reg = <0x30a50000 0x10000>; > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; @@ -1014,7 +1014,7 @@ bus at 0 or soc at 0 > + status = "disabled"; > + }; > + -> + uart4: serial at 30a60000 { +> + uart4: serial@30a60000 { > + compatible = "fsl,imx8mq-uart", > + "fsl,imx6q-uart"; > + reg = <0x30a60000 0x10000>; @@ -1025,7 +1025,7 @@ bus at 0 or soc at 0 > + status = "disabled"; > + }; > + -> + usdhc1: mmc at 30b40000 { +> + usdhc1: mmc@30b40000 { > + compatible = "fsl,imx8mq-usdhc", > + "fsl,imx7d-usdhc"; > + reg = <0x30b40000 0x10000>; @@ -1040,7 +1040,7 @@ bus at 0 or soc at 0 > + status = "disabled"; > + }; > + -> + usdhc2: mmc at 30b50000 { +> + usdhc2: mmc@30b50000 { > + compatible = "fsl,imx8mq-usdhc", > + "fsl,imx7d-usdhc"; > + reg = <0x30b50000 0x10000>; @@ -1055,7 +1055,7 @@ bus at 0 or soc at 0 > + status = "disabled"; > + }; > + -> + fec1: ethernet at 30be0000 { +> + fec1: ethernet@30be0000 { > + compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; > + reg = <0x30be0000 0x10000>; > + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, @@ -1074,7 +1074,7 @@ bus at 0 or soc at 0 > + }; > + }; > + -> + gic: interrupt-controller at 38800000 { +> + gic: interrupt-controller@38800000 { > + compatible = "arm,gic-v3"; > + reg = <0x38800000 0x10000>, /* GIC Dist */ > + <0x38880000 0xc0000>, /* GICR */ diff --git a/a/content_digest b/N1/content_digest index d0e0276..e1caed4 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,17 @@ "ref\020181114175242.12468-1-l.stach@pengutronix.de\0" "ref\020181114175242.12468-2-l.stach@pengutronix.de\0" - "From\0robh@kernel.org (Rob Herring)\0" - "Subject\0[PATCH v4 2/6] arm64: add basic DTS for i.MX8MQ\0" + "From\0Rob Herring <robh@kernel.org>\0" + "Subject\0Re: [PATCH v4 2/6] arm64: add basic DTS for i.MX8MQ\0" "Date\0Fri, 16 Nov 2018 17:25:24 -0600\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Lucas Stach <l.stach@pengutronix.de>\0" + "Cc\0A . s . Dong <aisheng.dong@nxp.com>" + devicetree@vger.kernel.org + patchwork-lst@pengutronix.de + NXP Linux Team <linux-imx@nxp.com> + kernel@pengutronix.de + Fabio Estevam <fabio.estevam@nxp.com> + Shawn Guo <shawnguo@kernel.org> + " linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Wed, Nov 14, 2018 at 06:52:38PM +0100, Lucas Stach wrote:\n" @@ -783,7 +791,7 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tA53_0: cpu at 0 {\n" + "> +\t\tA53_0: cpu@0 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a53\";\n" "> +\t\t\treg = <0x0>;\n" @@ -791,7 +799,7 @@ "> +\t\t\tnext-level-cache = <&A53_L2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tA53_1: cpu at 1 {\n" + "> +\t\tA53_1: cpu@1 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a53\";\n" "> +\t\t\treg = <0x1>;\n" @@ -799,7 +807,7 @@ "> +\t\t\tnext-level-cache = <&A53_L2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tA53_2: cpu at 2 {\n" + "> +\t\tA53_2: cpu@2 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a53\";\n" "> +\t\t\treg = <0x2>;\n" @@ -807,7 +815,7 @@ "> +\t\t\tnext-level-cache = <&A53_L2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tA53_3: cpu at 3 {\n" + "> +\t\tA53_3: cpu@3 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a53\";\n" "> +\t\t\treg = <0x3>;\n" @@ -835,22 +843,22 @@ "> +\t\tarm,no-tick-in-suspend;\n" "> +\t};\n" "> +\n" - "> +\tperipherals at 0 {\n" + "> +\tperipherals@0 {\n" "\n" - "bus at 0 or soc at 0\n" + "bus@0 or soc@0\n" "\n" "> +\t\tcompatible = \"simple-bus\";\n" "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <1>;\n" "> +\t\tranges = <0x0 0x0 0x0 0x3e000000>;\n" "> +\n" - "> +\t\tbus at 30000000 { /* AIPS1 */\n" + "> +\t\tbus@30000000 { /* AIPS1 */\n" "> +\t\t\tcompatible = \"fsl,imx8mq-aips-bus\", \"simple-bus\";\n" "> +\t\t\t#address-cells = <1>;\n" "> +\t\t\t#size-cells = <1>;\n" "> +\t\t\tranges = <0x30000000 0x30000000 0x400000>;\n" "> +\n" - "> +\t\t\tgpio1: gpio at 30200000 {\n" + "> +\t\t\tgpio1: gpio@30200000 {\n" "> +\t\t\t\tcompatible = \"fsl,imx8mq-gpio\", \"fsl,imx35-gpio\";\n" "> +\t\t\t\treg = <0x30200000 0x10000>;\n" "> +\t\t\t\tinterrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -861,7 +869,7 @@ "> +\t\t\t\t#interrupt-cells = <2>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tgpio2: gpio at 30210000 {\n" + "> +\t\t\tgpio2: gpio@30210000 {\n" "> +\t\t\t\tcompatible = \"fsl,imx8mq-gpio\", \"fsl,imx35-gpio\";\n" "> +\t\t\t\treg = <0x30210000 0x10000>;\n" "> +\t\t\t\tinterrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -872,7 +880,7 @@ "> +\t\t\t\t#interrupt-cells = <2>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tgpio3: gpio at 30220000 {\n" + "> +\t\t\tgpio3: gpio@30220000 {\n" "> +\t\t\t\tcompatible = \"fsl,imx8mq-gpio\", \"fsl,imx35-gpio\";\n" "> +\t\t\t\treg = <0x30220000 0x10000>;\n" "> +\t\t\t\tinterrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -883,7 +891,7 @@ "> +\t\t\t\t#interrupt-cells = <2>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tgpio4: gpio at 30230000 {\n" + "> +\t\t\tgpio4: gpio@30230000 {\n" "> +\t\t\t\tcompatible = \"fsl,imx8mq-gpio\", \"fsl,imx35-gpio\";\n" "> +\t\t\t\treg = <0x30230000 0x10000>;\n" "> +\t\t\t\tinterrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -894,7 +902,7 @@ "> +\t\t\t\t#interrupt-cells = <2>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tgpio5: gpio at 30240000 {\n" + "> +\t\t\tgpio5: gpio@30240000 {\n" "> +\t\t\t\tcompatible = \"fsl,imx8mq-gpio\", \"fsl,imx35-gpio\";\n" "> +\t\t\t\treg = <0x30240000 0x10000>;\n" "> +\t\t\t\tinterrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -905,23 +913,23 @@ "> +\t\t\t\t#interrupt-cells = <2>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tiomuxc: iomuxc at 30330000 {\n" + "> +\t\t\tiomuxc: iomuxc@30330000 {\n" "> +\t\t\t\tcompatible = \"fsl,imx8mq-iomuxc\";\n" "> +\t\t\t\treg = <0x30330000 0x10000>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tiomuxc_gpr: syscon at 30340000 {\n" + "> +\t\t\tiomuxc_gpr: syscon@30340000 {\n" "> +\t\t\t\tcompatible = \"fsl,imx8mq-iomuxc-gpr\", \"syscon\";\n" "> +\t\t\t\treg = <0x30340000 0x10000>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tanatop: syscon at 30360000 {\n" + "> +\t\t\tanatop: syscon@30360000 {\n" "> +\t\t\t\tcompatible = \"fsl,imx8mq-anatop\", \"syscon\";\n" "> +\t\t\t\treg = <0x30360000 0x10000>;\n" "> +\t\t\t\tinterrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tclk: clock-controller at 30380000 {\n" + "> +\t\t\tclk: clock-controller@30380000 {\n" "> +\t\t\t\tcompatible = \"fsl,imx8mq-ccm\";\n" "> +\t\t\t\treg = <0x30380000 0x10000>;\n" "> +\t\t\t\tinterrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -936,20 +944,20 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tbus at 30400000 { /* AIPS2 */\n" + "> +\t\tbus@30400000 { /* AIPS2 */\n" "> +\t\t\tcompatible = \"fsl,imx8mq-aips-bus\", \"simple-bus\";\n" "> +\t\t\t#address-cells = <1>;\n" "> +\t\t\t#size-cells = <1>;\n" "> +\t\t\tranges = <0x30400000 0x30400000 0x400000>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tbus at 30800000 { /* AIPS3 */\n" + "> +\t\tbus@30800000 { /* AIPS3 */\n" "> +\t\t\tcompatible = \"fsl,imx8mq-aips-bus\", \"simple-bus\";\n" "> +\t\t\t#address-cells = <1>;\n" "> +\t\t\t#size-cells = <1>;\n" "> +\t\t\tranges = <0x30800000 0x30800000 0x400000>;\n" "> +\n" - "> +\t\t\tuart1: serial at 30860000 {\n" + "> +\t\t\tuart1: serial@30860000 {\n" "> +\t\t\t\tcompatible = \"fsl,imx8mq-uart\",\n" "> +\t\t\t\t \"fsl,imx6q-uart\";\n" "> +\t\t\t\treg = <0x30860000 0x10000>;\n" @@ -960,7 +968,7 @@ "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart3: serial at 30880000 {\n" + "> +\t\t\tuart3: serial@30880000 {\n" "> +\t\t\t\tcompatible = \"fsl,imx8mq-uart\",\n" "> +\t\t\t\t \"fsl,imx6q-uart\";\n" "> +\t\t\t\treg = <0x30880000 0x10000>;\n" @@ -971,7 +979,7 @@ "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart2: serial at 30890000 {\n" + "> +\t\t\tuart2: serial@30890000 {\n" "> +\t\t\t\tcompatible = \"fsl,imx8mq-uart\",\n" "> +\t\t\t\t \"fsl,imx6q-uart\";\n" "> +\t\t\t\treg = <0x30890000 0x10000>;\n" @@ -982,7 +990,7 @@ "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ti2c1: i2c at 30a20000 {\n" + "> +\t\t\ti2c1: i2c@30a20000 {\n" "> +\t\t\t\tcompatible = \"fsl,imx8mq-i2c\", \"fsl,imx21-i2c\";\n" "> +\t\t\t\treg = <0x30a20000 0x10000>;\n" "> +\t\t\t\tinterrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -992,7 +1000,7 @@ "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ti2c2: i2c at 30a30000 {\n" + "> +\t\t\ti2c2: i2c@30a30000 {\n" "> +\t\t\t\tcompatible = \"fsl,imx8mq-i2c\", \"fsl,imx21-i2c\";\n" "> +\t\t\t\treg = <0x30a30000 0x10000>;\n" "> +\t\t\t\tinterrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -1002,7 +1010,7 @@ "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ti2c3: i2c at 30a40000 {\n" + "> +\t\t\ti2c3: i2c@30a40000 {\n" "> +\t\t\t\tcompatible = \"fsl,imx8mq-i2c\", \"fsl,imx21-i2c\";\n" "> +\t\t\t\treg = <0x30a40000 0x10000>;\n" "> +\t\t\t\tinterrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -1012,7 +1020,7 @@ "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ti2c4: i2c at 30a50000 {\n" + "> +\t\t\ti2c4: i2c@30a50000 {\n" "> +\t\t\t\tcompatible = \"fsl,imx8mq-i2c\", \"fsl,imx21-i2c\";\n" "> +\t\t\t\treg = <0x30a50000 0x10000>;\n" "> +\t\t\t\tinterrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -1022,7 +1030,7 @@ "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart4: serial at 30a60000 {\n" + "> +\t\t\tuart4: serial@30a60000 {\n" "> +\t\t\t\tcompatible = \"fsl,imx8mq-uart\",\n" "> +\t\t\t\t \"fsl,imx6q-uart\";\n" "> +\t\t\t\treg = <0x30a60000 0x10000>;\n" @@ -1033,7 +1041,7 @@ "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tusdhc1: mmc at 30b40000 {\n" + "> +\t\t\tusdhc1: mmc@30b40000 {\n" "> +\t\t\t\tcompatible = \"fsl,imx8mq-usdhc\",\n" "> +\t\t\t\t \"fsl,imx7d-usdhc\";\n" "> +\t\t\t\treg = <0x30b40000 0x10000>;\n" @@ -1048,7 +1056,7 @@ "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tusdhc2: mmc at 30b50000 {\n" + "> +\t\t\tusdhc2: mmc@30b50000 {\n" "> +\t\t\t\tcompatible = \"fsl,imx8mq-usdhc\",\n" "> +\t\t\t\t \"fsl,imx7d-usdhc\";\n" "> +\t\t\t\treg = <0x30b50000 0x10000>;\n" @@ -1063,7 +1071,7 @@ "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tfec1: ethernet at 30be0000 {\n" + "> +\t\t\tfec1: ethernet@30be0000 {\n" "> +\t\t\t\tcompatible = \"fsl,imx8mq-fec\", \"fsl,imx6sx-fec\";\n" "> +\t\t\t\treg = <0x30be0000 0x10000>;\n" "> +\t\t\t\tinterrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -1082,7 +1090,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tgic: interrupt-controller at 38800000 {\n" + "> +\t\tgic: interrupt-controller@38800000 {\n" "> +\t\t\tcompatible = \"arm,gic-v3\";\n" "> +\t\t\treg = <0x38800000 0x10000>,\t/* GIC Dist */\n" "> +\t\t\t <0x38880000 0xc0000>,\t/* GICR */\n" @@ -1100,4 +1108,4 @@ "> 2.19.1\n" > -6df67a72bd841c43ef608fd1691251ffb57a001eb3854b1792ee92d483654211 +73f53431882523258f58a804451c7bcbf8a5dcd608018cfb463f6321e4f3e983
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