From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.bootlin.com ([62.4.15.54]) by casper.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gOQwN-0007g4-SB for linux-mtd@lists.infradead.org; Sun, 18 Nov 2018 17:33:01 +0000 Date: Sun, 18 Nov 2018 18:32:48 +0100 From: Boris Brezillon To: Miquel Raynal Cc: David Woodhouse , Brian Norris , Marek Vasut , Richard Weinberger , linux-mtd@lists.infradead.org, Yogesh Gaur , Vignesh R , Cyrille Pitchen , Julien Su , Mark Brown , Mason Yang , linux-spi@vger.kernel.org, zhengxunli@mxic.com.tw Subject: Re: [PATCH RFC 05/18] spi: spi-mem: mxic: Add support for DTR and Octo mode Message-ID: <20181118183248.5ef63c04@bbrezillon> In-Reply-To: <20181118182111.3c199434@xps13> References: <20181012084825.23697-1-boris.brezillon@bootlin.com> <20181012084825.23697-6-boris.brezillon@bootlin.com> <20181118182111.3c199434@xps13> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Sun, 18 Nov 2018 18:21:11 +0100 Miquel Raynal wrote: > Hi Boris, >=20 > Boris Brezillon wrote on Fri, 12 Oct 2018 > 10:48:12 +0200: >=20 > > Signed-off-by: Boris Brezillon > > --- > > drivers/spi/spi-mxic.c | 27 +++++++++++++++++++++------ > > 1 file changed, 21 insertions(+), 6 deletions(-) > >=20 > > diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c > > index ce59ea2ecfe2..70e6bc9a099e 100644 > > --- a/drivers/spi/spi-mxic.c > > +++ b/drivers/spi/spi-mxic.c > > @@ -281,10 +281,11 @@ static int mxic_spi_data_xfer(struct mxic_spi *mx= ic, const void *txbuf, > > static bool mxic_spi_mem_supports_op(struct spi_mem *mem, > > const struct spi_mem_op *op) > > { > > - if (op->data.buswidth > 4 || op->addr.buswidth > 4 || > > - op->dummy.buswidth > 4 || op->cmd.buswidth > 4) > > + if (op->data.buswidth > 8 || op->addr.buswidth > 8 || > > + op->dummy.buswidth > 8 || op->cmd.buswidth > 8) > > return false; > > =20 > > + =20 >=20 > Extra space here >=20 > > if (op->data.nbytes && op->dummy.nbytes && > > op->data.buswidth !=3D op->dummy.buswidth) > > return false; > > @@ -302,6 +303,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem, > > int nio =3D 1, i, ret; > > u32 ss_ctrl; > > u8 addr[8]; > > + u8 cmd[2]; > > =20 > > ret =3D mxic_spi_clk_setup(mem->spi); > > if (ret) > > @@ -311,6 +313,8 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem, > > if (ret) > > return ret; > > =20 > > + if (mem->spi->mode & (SPI_RX_OCTO | SPI_TX_OCTO)) > > + nio =3D 8; > > if (mem->spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD)) > > nio =3D 4; > > else if (mem->spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL)) > > @@ -323,17 +327,21 @@ static int mxic_spi_mem_exec_op(struct spi_mem *m= em, > > mxic->regs + HC_CFG); > > writel(HC_EN_BIT, mxic->regs + HC_EN); > > =20 > > - ss_ctrl =3D OP_CMD_BYTES(1) | OP_CMD_BUSW(fls(op->cmd.buswidth) - 1); > > + ss_ctrl =3D OP_CMD_BYTES(op->cmd.nbytes) | > > + OP_CMD_BUSW(fls(op->cmd.buswidth) - 1) | > > + (op->cmd.dtr ? OP_CMD_DDR : 0); > > =20 > > if (op->addr.nbytes) > > ss_ctrl |=3D OP_ADDR_BYTES(op->addr.nbytes) | > > - OP_ADDR_BUSW(fls(op->addr.buswidth) - 1); > > + OP_ADDR_BUSW(fls(op->addr.buswidth) - 1) | > > + (op->addr.dtr ? OP_ADDR_DDR : 0); > > =20 > > if (op->dummy.nbytes) > > ss_ctrl |=3D OP_DUMMY_CYC(op->dummy.nbytes); > > =20 > > if (op->data.nbytes) { > > - ss_ctrl |=3D OP_DATA_BUSW(fls(op->data.buswidth) - 1); > > + ss_ctrl |=3D OP_DATA_BUSW(fls(op->data.buswidth) - 1) | > > + (op->data.dtr ? OP_DATA_DDR : 0); > > if (op->data.dir =3D=3D SPI_MEM_DATA_IN) > > ss_ctrl |=3D OP_READ; > > } > > @@ -343,7 +351,14 @@ static int mxic_spi_mem_exec_op(struct spi_mem *me= m, > > writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT, > > mxic->regs + HC_CFG); > > =20 > > - ret =3D mxic_spi_data_xfer(mxic, &op->cmd.opcode, NULL, 1); > > + if (op->cmd.nbytes =3D=3D 2) { > > + cmd[0] =3D op->cmd.opcode >> 8; > > + cmd[1] =3D op->cmd.opcode; > > + } else { > > + cmd[0] =3D op->cmd.opcode; > > + } =20 >=20 > I haven't played with this code yet and maybe I'll regret this but > wouldn't be easier for developers to have this in patch 4: >=20 > struct spi_mem_op { > struct { > + u8 nbytes; > u8 buswidth; > bool dtr; > - u8 opcode; > + u8 opcode[2]; /* <- an array of opcodes instead of an u16? */ Just wanted to stay consistent with what we have for the address cycles, but maybe I should clarify how the opcode should be transmitted on the wire (MSB first). > } cmd; >=20 > This way I think we would avoid endianness considerations and reading > would be eased. >=20 > > + > > + ret =3D mxic_spi_data_xfer(mxic, cmd, NULL, op->cmd.nbytes); > > if (ret) > > goto out; > > =20 >=20 >=20 > Thanks, > Miqu=C3=A8l From mboxrd@z Thu Jan 1 00:00:00 1970 From: Boris Brezillon Subject: Re: [PATCH RFC 05/18] spi: spi-mem: mxic: Add support for DTR and Octo mode Date: Sun, 18 Nov 2018 18:32:48 +0100 Message-ID: <20181118183248.5ef63c04@bbrezillon> References: <20181012084825.23697-1-boris.brezillon@bootlin.com> <20181012084825.23697-6-boris.brezillon@bootlin.com> <20181118182111.3c199434@xps13> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Cc: Yogesh Gaur , Vignesh R , Julien Su , Richard Weinberger , linux-spi@vger.kernel.org, Marek Vasut , Mark Brown , linux-mtd@lists.infradead.org, Mason Yang , Cyrille Pitchen , Brian Norris , David Woodhouse , zhengxunli@mxic.com.tw To: Miquel Raynal Return-path: In-Reply-To: <20181118182111.3c199434@xps13> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+gldm-linux-mtd-36=gmane.org@lists.infradead.org List-Id: linux-spi.vger.kernel.org T24gU3VuLCAxOCBOb3YgMjAxOCAxODoyMToxMSArMDEwMApNaXF1ZWwgUmF5bmFsIDxtaXF1ZWwu cmF5bmFsQGJvb3RsaW4uY29tPiB3cm90ZToKCj4gSGkgQm9yaXMsCj4gCj4gQm9yaXMgQnJlemls bG9uIDxib3Jpcy5icmV6aWxsb25AYm9vdGxpbi5jb20+IHdyb3RlIG9uIEZyaSwgMTIgT2N0IDIw MTgKPiAxMDo0ODoxMiArMDIwMDoKPiAKPiA+IFNpZ25lZC1vZmYtYnk6IEJvcmlzIEJyZXppbGxv biA8Ym9yaXMuYnJlemlsbG9uQGJvb3RsaW4uY29tPgo+ID4gLS0tCj4gPiAgZHJpdmVycy9zcGkv c3BpLW14aWMuYyB8IDI3ICsrKysrKysrKysrKysrKysrKysrKy0tLS0tLQo+ID4gIDEgZmlsZSBj aGFuZ2VkLCAyMSBpbnNlcnRpb25zKCspLCA2IGRlbGV0aW9ucygtKQo+ID4gCj4gPiBkaWZmIC0t Z2l0IGEvZHJpdmVycy9zcGkvc3BpLW14aWMuYyBiL2RyaXZlcnMvc3BpL3NwaS1teGljLmMKPiA+ IGluZGV4IGNlNTllYTJlY2ZlMi4uNzBlNmJjOWEwOTllIDEwMDY0NAo+ID4gLS0tIGEvZHJpdmVy cy9zcGkvc3BpLW14aWMuYwo+ID4gKysrIGIvZHJpdmVycy9zcGkvc3BpLW14aWMuYwo+ID4gQEAg LTI4MSwxMCArMjgxLDExIEBAIHN0YXRpYyBpbnQgbXhpY19zcGlfZGF0YV94ZmVyKHN0cnVjdCBt eGljX3NwaSAqbXhpYywgY29uc3Qgdm9pZCAqdHhidWYsCj4gPiAgc3RhdGljIGJvb2wgbXhpY19z cGlfbWVtX3N1cHBvcnRzX29wKHN0cnVjdCBzcGlfbWVtICptZW0sCj4gPiAgCQkJCSAgICAgY29u c3Qgc3RydWN0IHNwaV9tZW1fb3AgKm9wKQo+ID4gIHsKPiA+IC0JaWYgKG9wLT5kYXRhLmJ1c3dp ZHRoID4gNCB8fCBvcC0+YWRkci5idXN3aWR0aCA+IDQgfHwKPiA+IC0JICAgIG9wLT5kdW1teS5i dXN3aWR0aCA+IDQgfHwgb3AtPmNtZC5idXN3aWR0aCA+IDQpCj4gPiArCWlmIChvcC0+ZGF0YS5i dXN3aWR0aCA+IDggfHwgb3AtPmFkZHIuYnVzd2lkdGggPiA4IHx8Cj4gPiArCSAgICBvcC0+ZHVt bXkuYnVzd2lkdGggPiA4IHx8IG9wLT5jbWQuYnVzd2lkdGggPiA4KQo+ID4gIAkJcmV0dXJuIGZh bHNlOwo+ID4gIAo+ID4gKyAgCj4gCj4gRXh0cmEgc3BhY2UgaGVyZQo+IAo+ID4gIAlpZiAob3At PmRhdGEubmJ5dGVzICYmIG9wLT5kdW1teS5uYnl0ZXMgJiYKPiA+ICAJICAgIG9wLT5kYXRhLmJ1 c3dpZHRoICE9IG9wLT5kdW1teS5idXN3aWR0aCkKPiA+ICAJCXJldHVybiBmYWxzZTsKPiA+IEBA IC0zMDIsNiArMzAzLDcgQEAgc3RhdGljIGludCBteGljX3NwaV9tZW1fZXhlY19vcChzdHJ1Y3Qg c3BpX21lbSAqbWVtLAo+ID4gIAlpbnQgbmlvID0gMSwgaSwgcmV0Owo+ID4gIAl1MzIgc3NfY3Ry bDsKPiA+ICAJdTggYWRkcls4XTsKPiA+ICsJdTggY21kWzJdOwo+ID4gIAo+ID4gIAlyZXQgPSBt eGljX3NwaV9jbGtfc2V0dXAobWVtLT5zcGkpOwo+ID4gIAlpZiAocmV0KQo+ID4gQEAgLTMxMSw2 ICszMTMsOCBAQCBzdGF0aWMgaW50IG14aWNfc3BpX21lbV9leGVjX29wKHN0cnVjdCBzcGlfbWVt ICptZW0sCj4gPiAgCWlmIChyZXQpCj4gPiAgCQlyZXR1cm4gcmV0Owo+ID4gIAo+ID4gKwlpZiAo bWVtLT5zcGktPm1vZGUgJiAoU1BJX1JYX09DVE8gfCBTUElfVFhfT0NUTykpCj4gPiArCQluaW8g PSA4Owo+ID4gIAlpZiAobWVtLT5zcGktPm1vZGUgJiAoU1BJX1RYX1FVQUQgfCBTUElfUlhfUVVB RCkpCj4gPiAgCQluaW8gPSA0Owo+ID4gIAllbHNlIGlmIChtZW0tPnNwaS0+bW9kZSAmIChTUElf VFhfRFVBTCB8IFNQSV9SWF9EVUFMKSkKPiA+IEBAIC0zMjMsMTcgKzMyNywyMSBAQCBzdGF0aWMg aW50IG14aWNfc3BpX21lbV9leGVjX29wKHN0cnVjdCBzcGlfbWVtICptZW0sCj4gPiAgCSAgICAg ICBteGljLT5yZWdzICsgSENfQ0ZHKTsKPiA+ICAJd3JpdGVsKEhDX0VOX0JJVCwgbXhpYy0+cmVn cyArIEhDX0VOKTsKPiA+ICAKPiA+IC0Jc3NfY3RybCA9IE9QX0NNRF9CWVRFUygxKSB8IE9QX0NN RF9CVVNXKGZscyhvcC0+Y21kLmJ1c3dpZHRoKSAtIDEpOwo+ID4gKwlzc19jdHJsID0gT1BfQ01E X0JZVEVTKG9wLT5jbWQubmJ5dGVzKSB8Cj4gPiArCQkgIE9QX0NNRF9CVVNXKGZscyhvcC0+Y21k LmJ1c3dpZHRoKSAtIDEpIHwKPiA+ICsJCSAgKG9wLT5jbWQuZHRyID8gT1BfQ01EX0REUiA6IDAp Owo+ID4gIAo+ID4gIAlpZiAob3AtPmFkZHIubmJ5dGVzKQo+ID4gIAkJc3NfY3RybCB8PSBPUF9B RERSX0JZVEVTKG9wLT5hZGRyLm5ieXRlcykgfAo+ID4gLQkJCSAgIE9QX0FERFJfQlVTVyhmbHMo b3AtPmFkZHIuYnVzd2lkdGgpIC0gMSk7Cj4gPiArCQkJICAgT1BfQUREUl9CVVNXKGZscyhvcC0+ YWRkci5idXN3aWR0aCkgLSAxKSB8Cj4gPiArCQkJICAgKG9wLT5hZGRyLmR0ciA/IE9QX0FERFJf RERSIDogMCk7Cj4gPiAgCj4gPiAgCWlmIChvcC0+ZHVtbXkubmJ5dGVzKQo+ID4gIAkJc3NfY3Ry bCB8PSBPUF9EVU1NWV9DWUMob3AtPmR1bW15Lm5ieXRlcyk7Cj4gPiAgCj4gPiAgCWlmIChvcC0+ ZGF0YS5uYnl0ZXMpIHsKPiA+IC0JCXNzX2N0cmwgfD0gT1BfREFUQV9CVVNXKGZscyhvcC0+ZGF0 YS5idXN3aWR0aCkgLSAxKTsKPiA+ICsJCXNzX2N0cmwgfD0gT1BfREFUQV9CVVNXKGZscyhvcC0+ ZGF0YS5idXN3aWR0aCkgLSAxKSB8Cj4gPiArCQkJICAgKG9wLT5kYXRhLmR0ciA/IE9QX0RBVEFf RERSIDogMCk7Cj4gPiAgCQlpZiAob3AtPmRhdGEuZGlyID09IFNQSV9NRU1fREFUQV9JTikKPiA+ ICAJCQlzc19jdHJsIHw9IE9QX1JFQUQ7Cj4gPiAgCX0KPiA+IEBAIC0zNDMsNyArMzUxLDE0IEBA IHN0YXRpYyBpbnQgbXhpY19zcGlfbWVtX2V4ZWNfb3Aoc3RydWN0IHNwaV9tZW0gKm1lbSwKPiA+ ICAJd3JpdGVsKHJlYWRsKG14aWMtPnJlZ3MgKyBIQ19DRkcpIHwgSENfQ0ZHX01BTl9DU19BU1NF UlQsCj4gPiAgCSAgICAgICBteGljLT5yZWdzICsgSENfQ0ZHKTsKPiA+ICAKPiA+IC0JcmV0ID0g bXhpY19zcGlfZGF0YV94ZmVyKG14aWMsICZvcC0+Y21kLm9wY29kZSwgTlVMTCwgMSk7Cj4gPiAr CWlmIChvcC0+Y21kLm5ieXRlcyA9PSAyKSB7Cj4gPiArCQljbWRbMF0gPSBvcC0+Y21kLm9wY29k ZSA+PiA4Owo+ID4gKwkJY21kWzFdID0gb3AtPmNtZC5vcGNvZGU7Cj4gPiArCX0gZWxzZSB7Cj4g PiArCQljbWRbMF0gPSBvcC0+Y21kLm9wY29kZTsKPiA+ICsJfSAgCj4gCj4gSSBoYXZlbid0IHBs YXllZCB3aXRoIHRoaXMgY29kZSB5ZXQgYW5kIG1heWJlIEknbGwgcmVncmV0IHRoaXMgYnV0Cj4g d291bGRuJ3QgYmUgZWFzaWVyIGZvciBkZXZlbG9wZXJzIHRvIGhhdmUgdGhpcyBpbiBwYXRjaCA0 Ogo+IAo+ICBzdHJ1Y3Qgc3BpX21lbV9vcCB7Cj4gIAlzdHJ1Y3Qgewo+ICsJCXU4IG5ieXRlczsK PiAgCQl1OCBidXN3aWR0aDsKPiAgCQlib29sIGR0cjsKPiAtCQl1OCBvcGNvZGU7Cj4gKwkJdTgg b3Bjb2RlWzJdOyAvKiA8LSBhbiBhcnJheSBvZiBvcGNvZGVzIGluc3RlYWQgb2YgYW4gdTE2PyAq LwoKSnVzdCB3YW50ZWQgdG8gc3RheSBjb25zaXN0ZW50IHdpdGggd2hhdCB3ZSBoYXZlIGZvciB0 aGUgYWRkcmVzcwpjeWNsZXMsIGJ1dCBtYXliZSBJIHNob3VsZCBjbGFyaWZ5IGhvdyB0aGUgb3Bj b2RlIHNob3VsZCBiZQp0cmFuc21pdHRlZCBvbiB0aGUgd2lyZSAoTVNCIGZpcnN0KS4KCj4gIAl9 IGNtZDsKPiAKPiBUaGlzIHdheSBJIHRoaW5rIHdlIHdvdWxkIGF2b2lkIGVuZGlhbm5lc3MgY29u c2lkZXJhdGlvbnMgYW5kIHJlYWRpbmcKPiB3b3VsZCBiZSBlYXNlZC4KPiAKPiA+ICsKPiA+ICsJ cmV0ID0gbXhpY19zcGlfZGF0YV94ZmVyKG14aWMsIGNtZCwgTlVMTCwgb3AtPmNtZC5uYnl0ZXMp Owo+ID4gIAlpZiAocmV0KQo+ID4gIAkJZ290byBvdXQ7Cj4gPiAgICAKPiAKPiAKPiBUaGFua3Ms Cj4gTWlxdcOobAoKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fXwpMaW51eCBNVEQgZGlzY3Vzc2lvbiBtYWlsaW5nIGxpc3QKaHR0cDovL2xpc3Rz LmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1tdGQvCg==