From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: intel-gfx@lists.freedesktop.org, ville.syrjala@intel.com,
martin.peres@intel.com, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v12 1/2] drm: Introduce new DRM_FORMAT_XYUV
Date: Tue, 20 Nov 2018 16:27:21 +0200 [thread overview]
Message-ID: <20181120142720.GS9144@intel.com> (raw)
In-Reply-To: <20181109093916.25858-2-stanislav.lisovskiy@intel.com>
On Fri, Nov 09, 2018 at 11:39:15AM +0200, Stanislav Lisovskiy wrote:
> v5: This is YUV444 packed format same as AYUV, but without alpha,
> as supported by i915.
>
> v6: Removed unneeded initializer for new XYUV format.
>
> v7: Added is_yuv field initialization according to latest
> drm_fourcc format structure initialization changes.
>
> v8: Edited commit message to be more clear about skl+, renamed
> PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
> doesn't support per-pixel alpha. Fixed minor code issues.
>
> v9: Moved DRM format check to proper place in intel_framebuffer_init.
>
> v10: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV8888
>
> v11: Fixed rebase conflict, caused by added new formats to drm-tip
> meanwhile.
>
> Reviewed-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe@arm.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Pushed this one to drm-misc-next. Thanks for the patch and review.
The i915 part won't apply properly in drm-misc-next, so we'll need
to wait until dinq and drm-misc-next are suitably aligned before
we push that one.
> ---
> drivers/gpu/drm/drm_fourcc.c | 1 +
> include/uapi/drm/drm_fourcc.h | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index f523948c82b1..94d358eb0b8d 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -237,6 +237,7 @@ const struct drm_format_info *__drm_format_info(u32 format)
> { .format = DRM_FORMAT_X0L2, .depth = 0, .num_planes = 1,
> .char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 }, .block_h = { 2, 0, 0 },
> .hsub = 2, .vsub = 2, .is_yuv = true },
> + { .format = DRM_FORMAT_XYUV8888, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> };
>
> unsigned int i;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index e7e48f1f4a74..0b44260a5ee9 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -151,6 +151,7 @@ extern "C" {
> #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
>
> #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
> +#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
>
> /*
> * packed YCbCr420 2x2 tiled formats
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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Intel-gfx mailing list
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next prev parent reply other threads:[~2018-11-20 14:27 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-09 9:39 [PATCH v12 0/2] Add XYUV format support Stanislav Lisovskiy
2018-11-09 9:39 ` [PATCH v12 1/2] drm: Introduce new DRM_FORMAT_XYUV Stanislav Lisovskiy
2018-11-20 14:27 ` Ville Syrjälä [this message]
2019-07-26 17:36 ` Matt Roper
2018-11-09 9:39 ` [PATCH v12 2/2] drm/i915: Adding YUV444 packed format support for skl+ Stanislav Lisovskiy
2018-11-09 9:50 ` ✗ Fi.CI.CHECKPATCH: warning for Add XYUV format support (rev10) Patchwork
2018-11-09 10:15 ` ✗ Fi.CI.BAT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2018-11-08 11:46 [PATCH v12 0/2] Add XYUV format support Stanislav Lisovskiy
2018-11-08 11:46 ` [PATCH v12 1/2] drm: Introduce new DRM_FORMAT_XYUV Stanislav Lisovskiy
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