Re: [PATCH 3/7] drm/i915: Do not enable PSR in the next modeset after a error

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Fri, Nov 09, 2018 at 12:20:12PM -0800, José Roberto de Souza wrote:
> When we detect a error and disable PSR, it is kept disable until the
> next modeset but as the sink already show signs that it do not
> properly work with PSR lets disabled it for good to avoid any
> additional flickering.
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>

Maybe you can now just ignore my comment on the previous patch! :)

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>



> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  1 +
>  drivers/gpu/drm/i915/intel_psr.c | 10 +++++++++-
>  2 files changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 08d25aa480f7..e13222518c1b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -641,6 +641,7 @@ struct i915_psr {
>  	u8 sink_sync_latency;
>  	ktime_t last_entry_attempt;
>  	ktime_t last_exit;
> +	bool sink_not_reliable;
>  };
>  
>  enum intel_pch {
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index f940305b72e4..cc738497d551 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -508,6 +508,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
>  		return;
>  	}
>  
> +	if (dev_priv->psr.sink_not_reliable) {
> +		DRM_DEBUG_KMS("Sink not reliable set\n");
> +		return;
> +	}
> +
>  	if (IS_HASWELL(dev_priv) &&
>  	    I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) &
>  		      S3D_ENABLE) {
> @@ -1083,6 +1088,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
>  	if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR) {
>  		DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n");
>  		intel_psr_disable_locked(intel_dp);
> +		psr->sink_not_reliable = true;
>  	}
>  
>  	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) {
> @@ -1100,8 +1106,10 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
>  	if (val & ~errors)
>  		DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n",
>  			  val & ~errors);
> -	if (val & errors)
> +	if (val & errors) {
>  		intel_psr_disable_locked(intel_dp);
> +		psr->sink_not_reliable = true;
> +	}
>  	/* clear status register */
>  	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
>  exit:
> -- 
> 2.19.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx