From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 4/7] drm/i915: rename IS_GEN9_* to GT_GEN9_*
Date: Wed, 21 Nov 2018 14:22:56 -0800 [thread overview]
Message-ID: <20181121222256.GI13148@intel.com> (raw)
In-Reply-To: <20181106215123.27568-5-lucas.demarchi@intel.com>
On Tue, Nov 06, 2018 at 01:51:20PM -0800, Lucas De Marchi wrote:
> Like it was done for the generic IS_GEN -> GT_GEN rename, but since
> the LP/BC variants only exist in gen 9, keep the single macro
> definition. Also move the define to be together with GT_GEN().
>
> Users were converted with:
>
> sed -i 's/IS_GEN9_/GT_GEN9_/g' \
> drivers/gpu/drm/i915/*.{c,h} \
> drivers/gpu/drm/i915/*/*.{c,h}
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 22 ++++++-------
> drivers/gpu/drm/i915/i915_drv.c | 10 +++---
> drivers/gpu/drm/i915/i915_drv.h | 9 ++---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ++--
> drivers/gpu/drm/i915/i915_irq.c | 12 +++----
> drivers/gpu/drm/i915/i915_reg.h | 4 +--
> drivers/gpu/drm/i915/intel_bios.c | 4 +--
> drivers/gpu/drm/i915/intel_cdclk.c | 10 +++---
> drivers/gpu/drm/i915/intel_color.c | 2 +-
> drivers/gpu/drm/i915/intel_csr.c | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 42 ++++++++++++------------
> drivers/gpu/drm/i915/intel_device_info.c | 12 +++----
> drivers/gpu/drm/i915/intel_display.c | 18 +++++-----
> drivers/gpu/drm/i915/intel_dp.c | 28 ++++++++--------
> drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 +--
> drivers/gpu/drm/i915/intel_fbc.c | 2 +-
> drivers/gpu/drm/i915/intel_guc_fw.c | 2 +-
> drivers/gpu/drm/i915/intel_hdmi.c | 4 +--
> drivers/gpu/drm/i915/intel_i2c.c | 12 +++----
> drivers/gpu/drm/i915/intel_mocs.c | 4 +--
> drivers/gpu/drm/i915/intel_panel.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 18 +++++-----
> drivers/gpu/drm/i915/intel_runtime_pm.c | 22 ++++++-------
> drivers/gpu/drm/i915/intel_wopcm.c | 2 +-
> drivers/gpu/drm/i915/intel_workarounds.c | 4 +--
> drivers/gpu/drm/i915/vlv_dsi.c | 40 +++++++++++-----------
> 27 files changed, 150 insertions(+), 149 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 2514ec4d97d4..5e4a934c0dea 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1123,7 +1123,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> int max_freq;
>
> rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
> - if (IS_GEN9_LP(dev_priv)) {
> + if (GT_GEN9_LP(dev_priv)) {
> rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
> gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
> } else {
> @@ -1230,22 +1230,22 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> seq_printf(m, "Down threshold: %d%%\n",
> rps->power.down_threshold);
>
> - max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
> + max_freq = (GT_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
> rp_state_cap >> 16) & 0xff;
> - max_freq *= (IS_GEN9_BC(dev_priv) ||
> + max_freq *= (GT_GEN9_BC(dev_priv) ||
> INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
> seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
> intel_gpu_freq(dev_priv, max_freq));
>
> max_freq = (rp_state_cap & 0xff00) >> 8;
> - max_freq *= (IS_GEN9_BC(dev_priv) ||
> + max_freq *= (GT_GEN9_BC(dev_priv) ||
> INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
> seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
> intel_gpu_freq(dev_priv, max_freq));
>
> - max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
> + max_freq = (GT_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
> rp_state_cap >> 0) & 0xff;
> - max_freq *= (IS_GEN9_BC(dev_priv) ||
> + max_freq *= (GT_GEN9_BC(dev_priv) ||
> INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
> seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
> intel_gpu_freq(dev_priv, max_freq));
> @@ -1824,7 +1824,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
>
> min_gpu_freq = rps->min_freq;
> max_gpu_freq = rps->max_freq;
> - if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
> + if (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
> /* Convert GT frequency to 50 HZ units */
> min_gpu_freq /= GEN9_FREQ_SCALER;
> max_gpu_freq /= GEN9_FREQ_SCALER;
> @@ -1839,7 +1839,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
> &ia_freq);
> seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
> intel_gpu_freq(dev_priv, (gpu_freq *
> - (IS_GEN9_BC(dev_priv) ||
> + (GT_GEN9_BC(dev_priv) ||
> INTEL_GEN(dev_priv) >= 10 ?
> GEN9_FREQ_SCALER : 1))),
> ((ia_freq >> 0) & 0xff) * 100,
> @@ -2922,7 +2922,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> seq_printf(m, "DC3 -> DC5 count: %d\n",
> I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
> SKL_CSR_DC3_DC5_COUNT));
> - if (!IS_GEN9_LP(dev_priv))
> + if (!GT_GEN9_LP(dev_priv))
> seq_printf(m, "DC5 -> DC6 count: %d\n",
> I915_READ(SKL_CSR_DC5_DC6_COUNT));
>
> @@ -4423,14 +4423,14 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
>
> sseu->slice_mask |= BIT(s);
>
> - if (IS_GEN9_BC(dev_priv))
> + if (GT_GEN9_BC(dev_priv))
> sseu->subslice_mask[s] =
> INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
>
> for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> unsigned int eu_cnt;
>
> - if (IS_GEN9_LP(dev_priv)) {
> + if (GT_GEN9_LP(dev_priv)) {
> if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> /* skip disabled subslice */
> continue;
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index d2bdd7112c5d..8ff2acdec1f5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1322,7 +1322,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
> * This is only used for the level 0 watermark latency
> * w/a which does not apply to bxt/glk.
> */
> - dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
> + dram_info->is_16gb_dimm = !GT_GEN9_LP(dev_priv);
>
> if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv))
> return;
> @@ -1962,7 +1962,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
> get_suspend_mode(dev_priv, hibernation));
>
> ret = 0;
> - if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv))
> + if (INTEL_GEN(dev_priv) >= 11 || GT_GEN9_LP(dev_priv))
> bxt_enable_dc9(dev_priv);
> else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> hsw_enable_pc8(dev_priv);
> @@ -2152,7 +2152,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
>
> intel_uncore_resume_early(dev_priv);
>
> - if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 11 || GT_GEN9_LP(dev_priv)) {
> gen9_sanitize_dc_state(dev_priv);
> bxt_disable_dc9(dev_priv);
> } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> @@ -2922,7 +2922,7 @@ static int intel_runtime_suspend(struct device *kdev)
> if (INTEL_GEN(dev_priv) >= 11) {
> icl_display_core_uninit(dev_priv);
> bxt_enable_dc9(dev_priv);
> - } else if (IS_GEN9_LP(dev_priv)) {
> + } else if (GT_GEN9_LP(dev_priv)) {
> bxt_display_core_uninit(dev_priv);
> bxt_enable_dc9(dev_priv);
> } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> @@ -3018,7 +3018,7 @@ static int intel_runtime_resume(struct device *kdev)
> DC_STATE_EN_UPTO_DC5)
> gen9_enable_dc5(dev_priv);
> }
> - } else if (IS_GEN9_LP(dev_priv)) {
> + } else if (GT_GEN9_LP(dev_priv)) {
> bxt_disable_dc9(dev_priv);
> bxt_display_core_init(dev_priv, true);
> if (dev_priv->csr.dmc_payload &&
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f11aad5cd7fb..08c879f17b40 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2360,6 +2360,8 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define REVID_FOREVER 0xff
> #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
>
> +#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
> +
> #define GEN_FOREVER (0)
>
> #define INTEL_GEN_MASK(s, e) ( \
> @@ -2381,6 +2383,9 @@ intel_info(const struct drm_i915_private *dev_priv)
> (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
> (!!((dev_priv)->info.gen_mask & BIT((n) - 1))))
>
> +#define GT_GEN9_LP(dev_priv) (GT_GEN(dev_priv, 9) && IS_LP(dev_priv))
> +#define GT_GEN9_BC(dev_priv) (GT_GEN(dev_priv, 9) && !IS_LP(dev_priv))
> +
> /*
> * Return true if revision is in range [since,until] inclusive.
> *
> @@ -2532,10 +2537,6 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define IS_ICL_REVID(p, since, until) \
> (IS_ICELAKE(p) && IS_REVID(p, since, until))
>
> -#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
> -#define IS_GEN9_LP(dev_priv) (GT_GEN(dev_priv, 9) && IS_LP(dev_priv))
> -#define IS_GEN9_BC(dev_priv) (GT_GEN(dev_priv, 9) && !IS_LP(dev_priv))
> -
> #define ENGINE_MASK(id) BIT(id)
> #define RENDER_RING ENGINE_MASK(RCS)
> #define BSD_RING ENGINE_MASK(VCS)
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 1723f374c5a8..4ae6166c6593 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2168,7 +2168,7 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
> else if (IS_CHERRYVIEW(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> - else if (IS_GEN9_LP(dev_priv))
> + else if (GT_GEN9_LP(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
> else if (INTEL_GEN(dev_priv) >= 9)
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
> @@ -3002,7 +3002,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
> * resort to an uncached mapping. The WC issue is easily caught by the
> * readback check when writing GTT PTE entries.
> */
> - if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> + if (GT_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> ggtt->gsm = ioremap_nocache(phys_addr, size);
> else
> ggtt->gsm = ioremap_wc(phys_addr, size);
> @@ -3303,7 +3303,7 @@ static void setup_private_pat(struct drm_i915_private *dev_priv)
>
> if (INTEL_GEN(dev_priv) >= 10)
> cnl_setup_private_ppat(ppat);
> - else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
> + else if (IS_CHERRYVIEW(dev_priv) || GT_GEN9_LP(dev_priv))
> chv_setup_private_ppat(ppat);
> else
> bdw_setup_private_ppat(ppat);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 3ed545c2d508..e53e9ccf90f6 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2791,7 +2791,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> found = true;
> }
>
> - if (IS_GEN9_LP(dev_priv)) {
> + if (GT_GEN9_LP(dev_priv)) {
> tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
> if (tmp_mask) {
> bxt_hpd_irq_handler(dev_priv, tmp_mask,
> @@ -2807,7 +2807,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> }
> }
>
> - if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
> + if (GT_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
> gmbus_irq_handler(dev_priv);
> found = true;
> }
> @@ -4211,7 +4211,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
> de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
> GEN9_AUX_CHANNEL_D;
> - if (IS_GEN9_LP(dev_priv))
> + if (GT_GEN9_LP(dev_priv))
> de_port_masked |= BXT_DE_PORT_GMBUS;
> } else {
> de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> @@ -4227,7 +4227,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> GEN8_PIPE_FIFO_UNDERRUN;
>
> de_port_enables = de_port_masked;
> - if (IS_GEN9_LP(dev_priv))
> + if (GT_GEN9_LP(dev_priv))
> de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
> else if (IS_BROADWELL(dev_priv))
> de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
> @@ -4255,7 +4255,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>
> GEN3_IRQ_INIT(GEN11_DE_HPD_, ~de_hpd_masked, de_hpd_enables);
> gen11_hpd_detection_setup(dev_priv);
> - } else if (IS_GEN9_LP(dev_priv)) {
> + } else if (GT_GEN9_LP(dev_priv)) {
> bxt_hpd_detection_setup(dev_priv);
> } else if (IS_BROADWELL(dev_priv)) {
> ilk_hpd_detection_setup(dev_priv);
> @@ -4898,7 +4898,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> dev->driver->irq_uninstall = gen8_irq_reset;
> dev->driver->enable_vblank = gen8_enable_vblank;
> dev->driver->disable_vblank = gen8_disable_vblank;
> - if (IS_GEN9_LP(dev_priv))
> + if (GT_GEN9_LP(dev_priv))
> dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
> HAS_PCH_CNP(dev_priv))
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 158cf4716d03..33febd5a9eac 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3814,7 +3814,7 @@ enum i915_power_well_id {
> #define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
> #define INTERVAL_0_833_US(us) (((us) * 6) / 5)
> #define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
> - (IS_GEN9_LP(dev_priv) ? \
> + (GT_GEN9_LP(dev_priv) ? \
> INTERVAL_0_833_US(us) : \
> INTERVAL_1_33_US(us)) : \
> INTERVAL_1_28_US(us))
> @@ -3823,7 +3823,7 @@ enum i915_power_well_id {
> #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
> #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
> #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
> - (IS_GEN9_LP(dev_priv) ? \
> + (GT_GEN9_LP(dev_priv) ? \
> INTERVAL_0_833_TO_US(interval) : \
> INTERVAL_1_33_TO_US(interval)) : \
> INTERVAL_1_28_TO_US(interval))
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index fb918e942e9a..8fa3c79c5f4a 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -711,7 +711,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
> * Old decimal value is wake up time in multiples of 100 us.
> */
> if (bdb->version >= 205 &&
> - (IS_GEN9_BC(dev_priv) || IS_GEMINILAKE(dev_priv) ||
> + (GT_GEN9_BC(dev_priv) || IS_GEMINILAKE(dev_priv) ||
> INTEL_GEN(dev_priv) >= 10)) {
> switch (psr_table->tp1_wakeup_time) {
> case 0:
> @@ -2070,7 +2070,7 @@ intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
> const struct child_device_config *child;
> int i;
>
> - if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv)))
> + if (WARN_ON_ONCE(!GT_GEN9_LP(dev_priv)))
> return false;
>
> for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index db0edd01c973..37835d547d68 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -2565,7 +2565,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> dev_priv->max_cdclk_freq = 652800;
> } else if (IS_CANNONLAKE(dev_priv)) {
> dev_priv->max_cdclk_freq = 528000;
> - } else if (IS_GEN9_BC(dev_priv)) {
> + } else if (GT_GEN9_BC(dev_priv)) {
> u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
> int max_cdclk, vco;
>
> @@ -2775,11 +2775,11 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> dev_priv->display.set_cdclk = bdw_set_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> bdw_modeset_calc_cdclk;
> - } else if (IS_GEN9_LP(dev_priv)) {
> + } else if (GT_GEN9_LP(dev_priv)) {
> dev_priv->display.set_cdclk = bxt_set_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> bxt_modeset_calc_cdclk;
> - } else if (IS_GEN9_BC(dev_priv)) {
> + } else if (GT_GEN9_BC(dev_priv)) {
> dev_priv->display.set_cdclk = skl_set_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> skl_modeset_calc_cdclk;
> @@ -2796,9 +2796,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> dev_priv->display.get_cdclk = icl_get_cdclk;
> else if (IS_CANNONLAKE(dev_priv))
> dev_priv->display.get_cdclk = cnl_get_cdclk;
> - else if (IS_GEN9_BC(dev_priv))
> + else if (GT_GEN9_BC(dev_priv))
> dev_priv->display.get_cdclk = skl_get_cdclk;
> - else if (IS_GEN9_LP(dev_priv))
> + else if (GT_GEN9_LP(dev_priv))
> dev_priv->display.get_cdclk = bxt_get_cdclk;
> else if (IS_BROADWELL(dev_priv))
> dev_priv->display.get_cdclk = bdw_get_cdclk;
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 5127da286a2b..91a46e4f3453 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -655,7 +655,7 @@ void intel_color_init(struct drm_crtc *crtc)
> } else if (IS_HASWELL(dev_priv)) {
> dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
> dev_priv->display.load_luts = haswell_load_luts;
> - } else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
> + } else if (IS_BROADWELL(dev_priv) || GT_GEN9_BC(dev_priv) ||
> IS_BROXTON(dev_priv)) {
> dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
> dev_priv->display.load_luts = broadwell_load_luts;
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index fc7bd21fa586..2b5658143e19 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -232,7 +232,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
>
> mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
>
> - if (IS_GEN9_LP(dev_priv))
> + if (GT_GEN9_LP(dev_priv))
> mask |= DC_STATE_DEBUG_MASK_CORES;
>
> /* The below bit doesn't need to be cleared ever afterwards */
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index ab9a36c4ba3b..c8390eebe8e3 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -728,7 +728,7 @@ static const struct ddi_buf_trans *
> intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
> enum port port, int *n_entries)
> {
> - if (IS_GEN9_BC(dev_priv)) {
> + if (GT_GEN9_BC(dev_priv)) {
> const struct ddi_buf_trans *ddi_translations =
> skl_get_buf_trans_edp(dev_priv, n_entries);
> *n_entries = skl_buf_trans_num_entries(port, *n_entries);
> @@ -764,7 +764,7 @@ static const struct ddi_buf_trans *
> intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
> int *n_entries)
> {
> - if (IS_GEN9_BC(dev_priv)) {
> + if (GT_GEN9_BC(dev_priv)) {
> return skl_get_buf_trans_hdmi(dev_priv, n_entries);
> } else if (IS_BROADWELL(dev_priv)) {
> *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
> @@ -925,10 +925,10 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
> } else if (IS_CANNONLAKE(dev_priv)) {
> cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
> default_entry = n_entries - 1;
> - } else if (IS_GEN9_LP(dev_priv)) {
> + } else if (GT_GEN9_LP(dev_priv)) {
> bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
> default_entry = n_entries - 1;
> - } else if (IS_GEN9_BC(dev_priv)) {
> + } else if (GT_GEN9_BC(dev_priv)) {
> intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
> default_entry = 8;
> } else if (IS_BROADWELL(dev_priv)) {
> @@ -979,7 +979,7 @@ static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
> &n_entries);
>
> /* If we're boosting the current, set bit 31 of trans1 */
> - if (IS_GEN9_BC(dev_priv) &&
> + if (GT_GEN9_BC(dev_priv) &&
> dev_priv->vbt.ddi_port_info[port].dp_boost_level)
> iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
>
> @@ -1013,7 +1013,7 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
> level = n_entries - 1;
>
> /* If we're boosting the current, set bit 31 of trans1 */
> - if (IS_GEN9_BC(dev_priv) &&
> + if (GT_GEN9_BC(dev_priv) &&
> dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
> iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
>
> @@ -1741,9 +1741,9 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
> icl_ddi_clock_get(encoder, pipe_config);
> else if (IS_CANNONLAKE(dev_priv))
> cnl_ddi_clock_get(encoder, pipe_config);
> - else if (IS_GEN9_LP(dev_priv))
> + else if (GT_GEN9_LP(dev_priv))
> bxt_ddi_clock_get(encoder, pipe_config);
> - else if (IS_GEN9_BC(dev_priv))
> + else if (GT_GEN9_BC(dev_priv))
> skl_ddi_clock_get(encoder, pipe_config);
> else if (INTEL_GEN(dev_priv) <= 8)
> hsw_ddi_clock_get(encoder, pipe_config);
> @@ -2067,7 +2067,7 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
>
> out:
> - if (ret && IS_GEN9_LP(dev_priv)) {
> + if (ret && GT_GEN9_LP(dev_priv)) {
> tmp = I915_READ(BXT_PHY_CTL(port));
> if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
> BXT_PHY_LANE_POWERDOWN_ACK |
> @@ -2254,7 +2254,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
> cnl_get_buf_trans_edp(dev_priv, &n_entries);
> else
> cnl_get_buf_trans_dp(dev_priv, &n_entries);
> - } else if (IS_GEN9_LP(dev_priv)) {
> + } else if (GT_GEN9_LP(dev_priv)) {
> if (encoder->type == INTEL_OUTPUT_EDP)
> bxt_get_buf_trans_edp(dev_priv, &n_entries);
> else
> @@ -2736,7 +2736,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
> struct intel_encoder *encoder = &dport->base;
> int level = intel_ddi_dp_level(intel_dp);
>
> - if (IS_GEN9_BC(dev_priv))
> + if (GT_GEN9_BC(dev_priv))
> skl_ddi_set_iboost(encoder, level, encoder->type);
>
> return DDI_BUF_TRANS_SELECT(level);
> @@ -2877,7 +2877,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
> val = I915_READ(DPCLKA_CFGCR0);
> val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> I915_WRITE(DPCLKA_CFGCR0, val);
> - } else if (IS_GEN9_BC(dev_priv)) {
> + } else if (GT_GEN9_BC(dev_priv)) {
> /* DDI -> PLL mapping */
> val = I915_READ(DPLL_CTRL2);
>
> @@ -2906,7 +2906,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
> } else if (IS_CANNONLAKE(dev_priv)) {
> I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> DPCLKA_CFGCR0_DDI_CLK_OFF(port));
> - } else if (IS_GEN9_BC(dev_priv)) {
> + } else if (GT_GEN9_BC(dev_priv)) {
> I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
> DPLL_CTRL2_DDI_CLK_OFF(port));
> } else if (INTEL_GEN(dev_priv) < 9) {
> @@ -3075,7 +3075,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> level, encoder->type);
> else if (IS_CANNONLAKE(dev_priv))
> cnl_ddi_vswing_sequence(encoder, level, encoder->type);
> - else if (IS_GEN9_LP(dev_priv))
> + else if (GT_GEN9_LP(dev_priv))
> bxt_ddi_vswing_sequence(encoder, level, encoder->type);
> else
> intel_prepare_dp_ddi_buffers(encoder, crtc_state);
> @@ -3117,14 +3117,14 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
> level, INTEL_OUTPUT_HDMI);
> else if (IS_CANNONLAKE(dev_priv))
> cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
> - else if (IS_GEN9_LP(dev_priv))
> + else if (GT_GEN9_LP(dev_priv))
> bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
> else
> intel_prepare_hdmi_ddi_buffers(encoder, level);
>
> icl_enable_phy_clock_gating(dig_port);
>
> - if (IS_GEN9_BC(dev_priv))
> + if (GT_GEN9_BC(dev_priv))
> skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
>
> intel_ddi_enable_pipe_clock(crtc_state);
> @@ -3345,7 +3345,7 @@ static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
> connector->base.id, connector->name);
>
> /* Display WA #1143: skl,kbl,cfl */
> - if (IS_GEN9_BC(dev_priv)) {
> + if (GT_GEN9_BC(dev_priv)) {
> /*
> * For some reason these chicken bits have been
> * stuffed into a transcoder register, event though
> @@ -3500,7 +3500,7 @@ intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
> intel_display_power_get(dev_priv,
> intel_ddi_main_link_aux_domain(dig_port));
>
> - if (IS_GEN9_LP(dev_priv))
> + if (GT_GEN9_LP(dev_priv))
> bxt_ddi_phy_set_lane_optim_mask(encoder,
> crtc_state->lane_lat_optim_mask);
>
> @@ -3704,7 +3704,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>
> intel_ddi_clock_get(encoder, pipe_config);
>
> - if (IS_GEN9_LP(dev_priv))
> + if (GT_GEN9_LP(dev_priv))
> pipe_config->lane_lat_optim_mask =
> bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
>
> @@ -3745,7 +3745,7 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder,
> else
> ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
>
> - if (IS_GEN9_LP(dev_priv) && ret)
> + if (GT_GEN9_LP(dev_priv) && ret)
> pipe_config->lane_lat_optim_mask =
> bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
>
> @@ -3952,7 +3952,7 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
> /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
> * supported configuration
> */
> - if (IS_GEN9_LP(dev_priv))
> + if (GT_GEN9_LP(dev_priv))
> return true;
>
> /* Cannonlake: Most of SKUs don't support DDI_E, and the only
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 7f712cd238fe..ab967781f495 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -339,8 +339,8 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
> sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
>
> /* BXT has a single slice and at most 3 subslices. */
> - sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3;
> - sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4;
> + sseu->max_slices = GT_GEN9_LP(dev_priv) ? 1 : 3;
> + sseu->max_subslices = GT_GEN9_LP(dev_priv) ? 3 : 4;
> sseu->max_eus_per_subslice = 8;
>
> /*
> @@ -409,12 +409,12 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
> * pair per subslice.
> */
> sseu->has_slice_pg =
> - !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1;
> + !GT_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1;
> sseu->has_subslice_pg =
> - IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1;
> + GT_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1;
> sseu->has_eu_pg = sseu->eu_per_subslice > 2;
>
> - if (IS_GEN9_LP(dev_priv)) {
> + if (GT_GEN9_LP(dev_priv)) {
> #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
> info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
>
> @@ -671,7 +671,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
> if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
> freq = read_reference_ts_freq(dev_priv);
> } else {
> - freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz;
> + freq = GT_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz;
>
> /* Now figure out how the command stream's timestamp
> * register increments from this frequency (it might
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 904950a65c1b..b13956966a58 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -556,12 +556,12 @@ static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
> INTELPllInvalid("m1 out of range\n");
>
> if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
> - !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
> + !IS_CHERRYVIEW(dev_priv) && !GT_GEN9_LP(dev_priv))
> if (clock->m1 <= clock->m2)
> INTELPllInvalid("m1 <= m2\n");
>
> if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> - !IS_GEN9_LP(dev_priv)) {
> + !GT_GEN9_LP(dev_priv)) {
> if (clock->p < limit->p.min || limit->p.max < clock->p)
> INTELPllInvalid("p out of range\n");
> if (clock->m < limit->m.min || limit->m.max < clock->m)
> @@ -9481,9 +9481,9 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
> icelake_get_ddi_pll(dev_priv, port, pipe_config);
> else if (IS_CANNONLAKE(dev_priv))
> cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
> - else if (IS_GEN9_BC(dev_priv))
> + else if (GT_GEN9_BC(dev_priv))
> skylake_get_ddi_pll(dev_priv, port, pipe_config);
> - else if (IS_GEN9_LP(dev_priv))
> + else if (GT_GEN9_LP(dev_priv))
> bxt_get_ddi_pll(dev_priv, port, pipe_config);
> else
> haswell_get_ddi_pll(dev_priv, port, pipe_config);
> @@ -9530,7 +9530,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
>
> active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
>
> - if (IS_GEN9_LP(dev_priv) &&
> + if (GT_GEN9_LP(dev_priv) &&
> bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
> WARN_ON(active);
> active = true;
> @@ -14101,7 +14101,7 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
>
> static void intel_pps_init(struct drm_i915_private *dev_priv)
> {
> - if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
> + if (HAS_PCH_SPLIT(dev_priv) || GT_GEN9_LP(dev_priv))
> dev_priv->pps_mmio_base = PCH_PPS_BASE;
> else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> dev_priv->pps_mmio_base = VLV_PPS_BASE;
> @@ -14139,7 +14139,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> intel_ddi_init(dev_priv, PORT_E);
> intel_ddi_init(dev_priv, PORT_F);
> icl_dsi_init(dev_priv);
> - } else if (IS_GEN9_LP(dev_priv)) {
> + } else if (GT_GEN9_LP(dev_priv)) {
> /*
> * FIXME: Broxton doesn't support port detection via the
> * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
> @@ -14160,7 +14160,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> */
> found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
> /* WaIgnoreDDIAStrap: skl */
> - if (found || IS_GEN9_BC(dev_priv))
> + if (found || GT_GEN9_BC(dev_priv))
> intel_ddi_init(dev_priv, PORT_A);
>
> /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
> @@ -14178,7 +14178,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> /*
> * On SKL we don't have a way to detect DDI-E so we rely on VBT.
> */
> - if (IS_GEN9_BC(dev_priv) &&
> + if (GT_GEN9_BC(dev_priv) &&
> (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
> dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
> dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 9e410b04f99d..7f6ceb00574f 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -346,10 +346,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> max_rate = cnl_max_source_rate(intel_dp);
> else
> max_rate = icl_max_source_rate(intel_dp);
> - } else if (IS_GEN9_LP(dev_priv)) {
> + } else if (GT_GEN9_LP(dev_priv)) {
> source_rates = bxt_rates;
> size = ARRAY_SIZE(bxt_rates);
> - } else if (IS_GEN9_BC(dev_priv)) {
> + } else if (GT_GEN9_BC(dev_priv)) {
> source_rates = skl_rates;
> size = ARRAY_SIZE(skl_rates);
> } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
> @@ -884,7 +884,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
> struct intel_encoder *encoder;
>
> if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> - !IS_GEN9_LP(dev_priv)))
> + !GT_GEN9_LP(dev_priv)))
> return;
>
> /*
> @@ -905,7 +905,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
> if (encoder->type != INTEL_OUTPUT_EDP)
> continue;
>
> - if (IS_GEN9_LP(dev_priv))
> + if (GT_GEN9_LP(dev_priv))
> intel_dp->pps_reset = true;
> else
> intel_dp->pps_pipe = INVALID_PIPE;
> @@ -928,7 +928,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
>
> memset(regs, 0, sizeof(*regs));
>
> - if (IS_GEN9_LP(dev_priv))
> + if (GT_GEN9_LP(dev_priv))
> pps_idx = bxt_power_sequencer_idx(intel_dp);
> else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> pps_idx = vlv_power_sequencer_pipe(intel_dp);
> @@ -937,7 +937,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
> regs->pp_stat = PP_STATUS(pps_idx);
> regs->pp_on = PP_ON_DELAYS(pps_idx);
> regs->pp_off = PP_OFF_DELAYS(pps_idx);
> - if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
> + if (!GT_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
> !HAS_PCH_ICP(dev_priv))
> regs->pp_div = PP_DIVISOR(pps_idx);
> }
> @@ -3648,7 +3648,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> uint32_t signal_levels, mask = 0;
> uint8_t train_set = intel_dp->train_set[0];
>
> - if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
> + if (GT_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
> signal_levels = bxt_signal_levels(intel_dp);
> } else if (HAS_DDI(dev_priv)) {
> signal_levels = ddi_signal_levels(intel_dp);
> @@ -5026,9 +5026,9 @@ bool intel_digital_port_connected(struct intel_encoder *encoder)
>
> if (INTEL_GEN(dev_priv) >= 11)
> return icl_digital_port_connected(encoder);
> - else if (GT_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv))
> + else if (GT_GEN(dev_priv, 10) || GT_GEN9_BC(dev_priv))
> return spt_digital_port_connected(encoder);
> - else if (IS_GEN9_LP(dev_priv))
> + else if (GT_GEN9_LP(dev_priv))
> return bxt_digital_port_connected(encoder);
> else if (GT_GEN(dev_priv, 8))
> return bdw_digital_port_connected(encoder);
> @@ -5780,7 +5780,7 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
>
> pp_on = I915_READ(regs.pp_on);
> pp_off = I915_READ(regs.pp_off);
> - if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
> + if (!GT_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
> !HAS_PCH_ICP(dev_priv)) {
> I915_WRITE(regs.pp_ctrl, pp_ctl);
> pp_div = I915_READ(regs.pp_div);
> @@ -5799,7 +5799,7 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
> seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> PANEL_POWER_DOWN_DELAY_SHIFT;
>
> - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
> + if (GT_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
> HAS_PCH_ICP(dev_priv)) {
> seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
> @@ -5971,7 +5971,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
> (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> /* Compute the divisor for the pp clock, simply match the Bspec
> * formula. */
> - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
> + if (GT_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
> HAS_PCH_ICP(dev_priv)) {
> pp_div = I915_READ(regs.pp_ctrl);
> pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
> @@ -6008,7 +6008,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
>
> I915_WRITE(regs.pp_on, pp_on);
> I915_WRITE(regs.pp_off, pp_off);
> - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
> + if (GT_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
> HAS_PCH_ICP(dev_priv))
> I915_WRITE(regs.pp_ctrl, pp_div);
> else
> @@ -6017,7 +6017,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
> DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> I915_READ(regs.pp_on),
> I915_READ(regs.pp_off),
> - (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
> + (GT_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
> HAS_PCH_ICP(dev_priv)) ?
> (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
> I915_READ(regs.pp_div));
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 8b71d64ebd9d..9bf8b86c60df 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -98,7 +98,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
>
> pipe_config->dp_m_n.tu = slots;
>
> - if (IS_GEN9_LP(dev_priv))
> + if (GT_GEN9_LP(dev_priv))
> pipe_config->lane_lat_optim_mask =
> bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 901e15063b24..5d756fdd1e7e 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -3212,9 +3212,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
> dpll_mgr = &icl_pll_mgr;
> else if (IS_CANNONLAKE(dev_priv))
> dpll_mgr = &cnl_pll_mgr;
> - else if (IS_GEN9_BC(dev_priv))
> + else if (GT_GEN9_BC(dev_priv))
> dpll_mgr = &skl_pll_mgr;
> - else if (IS_GEN9_LP(dev_priv))
> + else if (GT_GEN9_LP(dev_priv))
> dpll_mgr = &bxt_pll_mgr;
> else if (HAS_DDI(dev_priv))
> dpll_mgr = &hsw_pll_mgr;
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index 549e3dc0e457..7ed976ada979 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -444,7 +444,7 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv,
> * reserved range size, so it always assumes the maximum (8mb) is used.
> * If we enable FBC using a CFB on that memory range we'll get FIFO
> * underruns, even if that range is not reserved by the BIOS. */
> - if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv))
> + if (IS_BROADWELL(dev_priv) || GT_GEN9_BC(dev_priv))
> end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024;
> else
> end = U64_MAX;
> diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
> index 9fdce47755e2..586f435633c7 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_guc_fw.c
> @@ -109,7 +109,7 @@ static void guc_prepare_xfer(struct intel_guc *guc)
> GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
> GUC_ENABLE_MIA_CLOCK_GATING);
>
> - if (IS_GEN9_LP(dev_priv))
> + if (GT_GEN9_LP(dev_priv))
> I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
> else
> I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index bc5b945f9a71..f954c2883f92 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1529,7 +1529,7 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> return MODE_CLOCK_HIGH;
>
> /* BXT DPLL can't generate 223-240 MHz */
> - if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
> + if (GT_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
> return MODE_CLOCK_RANGE;
>
> /* CHV DPLL can't generate 216-240 MHz */
> @@ -2321,7 +2321,7 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
>
> if (IS_CHERRYVIEW(dev_priv))
> ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
> - else if (IS_GEN9_LP(dev_priv))
> + else if (GT_GEN9_LP(dev_priv))
> ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
> else if (HAS_PCH_CNP(dev_priv))
> ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index 33d87ab93fdd..86d898844a97 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -93,9 +93,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
> return &gmbus_pins_icp[pin];
> else if (HAS_PCH_CNP(dev_priv))
> return &gmbus_pins_cnp[pin];
> - else if (IS_GEN9_LP(dev_priv))
> + else if (GT_GEN9_LP(dev_priv))
> return &gmbus_pins_bxt[pin];
> - else if (IS_GEN9_BC(dev_priv))
> + else if (GT_GEN9_BC(dev_priv))
> return &gmbus_pins_skl[pin];
> else if (IS_BROADWELL(dev_priv))
> return &gmbus_pins_bdw[pin];
> @@ -112,9 +112,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
> size = ARRAY_SIZE(gmbus_pins_icp);
> else if (HAS_PCH_CNP(dev_priv))
> size = ARRAY_SIZE(gmbus_pins_cnp);
> - else if (IS_GEN9_LP(dev_priv))
> + else if (GT_GEN9_LP(dev_priv))
> size = ARRAY_SIZE(gmbus_pins_bxt);
> - else if (IS_GEN9_BC(dev_priv))
> + else if (GT_GEN9_BC(dev_priv))
> size = ARRAY_SIZE(gmbus_pins_skl);
> else if (IS_BROADWELL(dev_priv))
> size = ARRAY_SIZE(gmbus_pins_bdw);
> @@ -576,7 +576,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
> int ret = 0;
>
> /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
> - if (IS_GEN9_LP(dev_priv))
> + if (GT_GEN9_LP(dev_priv))
> bxt_gmbus_clock_gating(dev_priv, false);
> else if (HAS_PCH_SPT(dev_priv) ||
> HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv))
> @@ -686,7 +686,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
>
> out:
> /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
> - if (IS_GEN9_LP(dev_priv))
> + if (GT_GEN9_LP(dev_priv))
> bxt_gmbus_clock_gating(dev_priv, true);
> else if (HAS_PCH_SPT(dev_priv) ||
> HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index 8201774c2c0f..6b9076fd5836 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -178,12 +178,12 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
> {
> bool result = false;
>
> - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) ||
> + if (GT_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) ||
> IS_ICELAKE(dev_priv)) {
> table->size = ARRAY_SIZE(skylake_mocs_table);
> table->table = skylake_mocs_table;
> result = true;
> - } else if (IS_GEN9_LP(dev_priv)) {
> + } else if (GT_GEN9_LP(dev_priv)) {
> table->size = ARRAY_SIZE(broxton_mocs_table);
> table->table = broxton_mocs_table;
> result = true;
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index e658904c5576..78d5b9da3a02 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -1839,7 +1839,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
> intel_dsi_dcs_init_backlight_funcs(connector) == 0)
> return;
>
> - if (IS_GEN9_LP(dev_priv)) {
> + if (GT_GEN9_LP(dev_priv)) {
> panel->backlight.setup = bxt_setup_backlight;
> panel->backlight.enable = bxt_enable_backlight;
> panel->backlight.disable = bxt_disable_backlight;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 74e14d8848f8..3a321600bb78 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3602,7 +3602,7 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>
> - if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
> + if (GT_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
> return true;
>
> return false;
> @@ -3611,7 +3611,7 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
> static bool
> intel_has_sagv(struct drm_i915_private *dev_priv)
> {
> - return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
> + return (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
> dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
> }
>
> @@ -6894,7 +6894,7 @@ static bool sanitize_rc6(struct drm_i915_private *i915)
> info->has_rc6 = 0;
>
> if (info->has_rc6 &&
> - IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(i915)) {
> + GT_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(i915)) {
> DRM_INFO("RC6 disabled by BIOS\n");
> info->has_rc6 = 0;
> }
> @@ -6918,7 +6918,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
> /* All of these values are in units of 50MHz */
>
> /* static values from HW: RP0 > RP1 > RPn (min_freq) */
> - if (IS_GEN9_LP(dev_priv)) {
> + if (GT_GEN9_LP(dev_priv)) {
> u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
> rps->rp0_freq = (rp_state_cap >> 16) & 0xff;
> rps->rp1_freq = (rp_state_cap >> 8) & 0xff;
> @@ -6934,7 +6934,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
>
> rps->efficient_freq = rps->rp1_freq;
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
> - IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
> + GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
> u32 ddcc_status = 0;
>
> if (sandybridge_pcode_read(dev_priv,
> @@ -6947,7 +6947,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
> rps->max_freq);
> }
>
> - if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
> + if (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
> /* Store the frequency values in 16.66 MHZ units, which is
> * the natural hardware unit for SKL
> */
> @@ -7285,7 +7285,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
>
> min_gpu_freq = rps->min_freq;
> max_gpu_freq = rps->max_freq;
> - if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
> + if (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
> /* Convert GT frequency to 50 HZ units */
> min_gpu_freq /= GEN9_FREQ_SCALER;
> max_gpu_freq /= GEN9_FREQ_SCALER;
> @@ -7300,7 +7300,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
> const int diff = max_gpu_freq - gpu_freq;
> unsigned int ia_freq = 0, ring_freq = 0;
>
> - if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
> + if (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
> /*
> * ring_freq = 2 * GT. ring_freq is in 100MHz units
> * No floor required for ring frequency on SKL.
> @@ -9885,7 +9885,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
> time_hw = vlv_residency_raw(dev_priv, reg);
> } else {
> /* 833.33ns units on Gen9LP, 1.28us elsewhere. */
> - if (IS_GEN9_LP(dev_priv)) {
> + if (GT_GEN9_LP(dev_priv)) {
> mul = 10000;
> div = 12;
> } else {
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index b164a2c4b058..3b78afe0a790 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -581,7 +581,7 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
> mask = DC_STATE_EN_UPTO_DC5;
> if (INTEL_GEN(dev_priv) >= 11)
> mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
> - else if (IS_GEN9_LP(dev_priv))
> + else if (GT_GEN9_LP(dev_priv))
> mask |= DC_STATE_EN_DC9;
> else
> mask |= DC_STATE_EN_UPTO_DC6;
> @@ -725,7 +725,7 @@ void gen9_enable_dc5(struct drm_i915_private *dev_priv)
> DRM_DEBUG_KMS("Enabling DC5\n");
>
> /* Wa Display #1183: skl,kbl,cfl */
> - if (IS_GEN9_BC(dev_priv))
> + if (GT_GEN9_BC(dev_priv))
> I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
> SKL_SELECT_ALTERNATE_DC_EXIT);
>
> @@ -749,7 +749,7 @@ void skl_enable_dc6(struct drm_i915_private *dev_priv)
> DRM_DEBUG_KMS("Enabling DC6\n");
>
> /* Wa Display #1183: skl,kbl,cfl */
> - if (IS_GEN9_BC(dev_priv))
> + if (GT_GEN9_BC(dev_priv))
> I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
> SKL_SELECT_ALTERNATE_DC_EXIT);
>
> @@ -841,7 +841,7 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
>
> gen9_assert_dbuf_enabled(dev_priv);
>
> - if (IS_GEN9_LP(dev_priv))
> + if (GT_GEN9_LP(dev_priv))
> bxt_verify_ddi_phy_power_wells(dev_priv);
> }
>
> @@ -3027,10 +3027,10 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
> * suspend/resume, so allow it unconditionally.
> */
> mask = DC_STATE_EN_DC9;
> - } else if (GT_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) {
> + } else if (GT_GEN(dev_priv, 10) || GT_GEN9_BC(dev_priv)) {
> max_dc = 2;
> mask = 0;
> - } else if (IS_GEN9_LP(dev_priv)) {
> + } else if (GT_GEN9_LP(dev_priv)) {
> max_dc = 1;
> mask = DC_STATE_EN_DC9;
> } else {
> @@ -3143,7 +3143,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> err = set_power_wells(power_domains, glk_power_wells);
> } else if (IS_BROXTON(dev_priv)) {
> err = set_power_wells(power_domains, bxt_power_wells);
> - } else if (IS_GEN9_BC(dev_priv)) {
> + } else if (GT_GEN9_BC(dev_priv)) {
> err = set_power_wells(power_domains, skl_power_wells);
> } else if (IS_CHERRYVIEW(dev_priv)) {
> err = set_power_wells(power_domains, chv_power_wells);
> @@ -3814,9 +3814,9 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
> icl_display_core_init(dev_priv, resume);
> } else if (IS_CANNONLAKE(dev_priv)) {
> cnl_display_core_init(dev_priv, resume);
> - } else if (IS_GEN9_BC(dev_priv)) {
> + } else if (GT_GEN9_BC(dev_priv)) {
> skl_display_core_init(dev_priv, resume);
> - } else if (IS_GEN9_LP(dev_priv)) {
> + } else if (GT_GEN9_LP(dev_priv)) {
> bxt_display_core_init(dev_priv, resume);
> } else if (IS_CHERRYVIEW(dev_priv)) {
> mutex_lock(&power_domains->lock);
> @@ -3945,9 +3945,9 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
> icl_display_core_uninit(dev_priv);
> else if (IS_CANNONLAKE(dev_priv))
> cnl_display_core_uninit(dev_priv);
> - else if (IS_GEN9_BC(dev_priv))
> + else if (GT_GEN9_BC(dev_priv))
> skl_display_core_uninit(dev_priv);
> - else if (IS_GEN9_LP(dev_priv))
> + else if (GT_GEN9_LP(dev_priv))
> bxt_display_core_uninit(dev_priv);
>
> power_domains->display_core_suspended = true;
> diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c
> index 3987207cddd0..0a5c68acf3dd 100644
> --- a/drivers/gpu/drm/i915/intel_wopcm.c
> +++ b/drivers/gpu/drm/i915/intel_wopcm.c
> @@ -78,7 +78,7 @@ void intel_wopcm_init_early(struct intel_wopcm *wopcm)
>
> static inline u32 context_reserved_size(struct drm_i915_private *i915)
> {
> - if (IS_GEN9_LP(i915))
> + if (GT_GEN9_LP(i915))
> return BXT_WOPCM_RC6_CTX_RESERVED;
> else if (INTEL_GEN(i915) >= 10)
> return CNL_WOPCM_HW_CTX_RESERVED;
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index d7176213e3ce..db899cc5c981 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -300,7 +300,7 @@ static int gen9_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
>
> /* WaClearHIZ_WM_CHICKEN3:bxt,glk */
> - if (IS_GEN9_LP(dev_priv))
> + if (GT_GEN9_LP(dev_priv))
> WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
>
> return 0;
> @@ -620,7 +620,7 @@ static void gen9_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> BDW_DISABLE_HDC_INVALIDATION);
>
> /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
> - if (IS_GEN9_LP(dev_priv)) {
> + if (GT_GEN9_LP(dev_priv)) {
> u32 val = I915_READ(GEN8_L3SQCREG1);
>
> val &= ~L3_PRIO_CREDITS_MASK;
> diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
> index bab87b62bc2d..a06221dca0ec 100644
> --- a/drivers/gpu/drm/i915/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/vlv_dsi.c
> @@ -290,7 +290,7 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
> /* DSI uses short packets for sync events, so clear mode flags for DSI */
> adjusted_mode->flags = 0;
>
> - if (IS_GEN9_LP(dev_priv)) {
> + if (GT_GEN9_LP(dev_priv)) {
> /* Enable Frame time stamp based scanline reporting */
> adjusted_mode->private_flags |=
> I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
> @@ -510,7 +510,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
>
> if (IS_GEMINILAKE(dev_priv))
> glk_dsi_device_ready(encoder);
> - else if (IS_GEN9_LP(dev_priv))
> + else if (GT_GEN9_LP(dev_priv))
> bxt_dsi_device_ready(encoder);
> else
> vlv_dsi_device_ready(encoder);
> @@ -591,7 +591,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
> DRM_DEBUG_KMS("\n");
> for_each_dsi_port(port, intel_dsi->ports) {
> /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
> - i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
> + i915_reg_t port_ctrl = GT_GEN9_LP(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
> u32 val;
>
> @@ -611,7 +611,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
> * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
> * Port A only. MIPI Port C has no similar bit for checking.
> */
> - if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
> + if ((GT_GEN9_LP(dev_priv) || port == PORT_A) &&
> intel_wait_for_register(dev_priv,
> port_ctrl, AFE_LATCHOUT, 0,
> 30))
> @@ -637,7 +637,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder,
>
> if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> u32 temp;
> - if (IS_GEN9_LP(dev_priv)) {
> + if (GT_GEN9_LP(dev_priv)) {
> for_each_dsi_port(port, intel_dsi->ports) {
> temp = I915_READ(MIPI_CTRL(port));
> temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
> @@ -655,7 +655,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder,
> }
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
> + i915_reg_t port_ctrl = GT_GEN9_LP(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> u32 temp;
>
> @@ -688,7 +688,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
> enum port port;
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
> + i915_reg_t port_ctrl = GT_GEN9_LP(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> u32 temp;
>
> @@ -765,7 +765,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
> * The BIOS may leave the PLL in a wonky state where it doesn't
> * lock. It needs to be fully powered down to fix it.
> */
> - if (IS_GEN9_LP(dev_priv)) {
> + if (GT_GEN9_LP(dev_priv)) {
> bxt_dsi_pll_disable(encoder);
> bxt_dsi_pll_enable(encoder, pipe_config);
> } else {
> @@ -927,7 +927,7 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder,
> val & ~MIPIO_RST_CTRL);
> }
>
> - if (IS_GEN9_LP(dev_priv)) {
> + if (GT_GEN9_LP(dev_priv)) {
> bxt_dsi_pll_disable(encoder);
> } else {
> u32 val;
> @@ -974,12 +974,12 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
> * configuration, otherwise accessing DSI registers will hang the
> * machine. See BSpec North Display Engine registers/MIPI[BXT].
> */
> - if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv))
> + if (GT_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv))
> goto out_put_power;
>
> /* XXX: this only works for one DSI output */
> for_each_dsi_port(port, intel_dsi->ports) {
> - i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
> + i915_reg_t ctrl_reg = GT_GEN9_LP(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
>
> @@ -1004,7 +1004,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
> if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
> continue;
>
> - if (IS_GEN9_LP(dev_priv)) {
> + if (GT_GEN9_LP(dev_priv)) {
> u32 tmp = I915_READ(MIPI_CTRL(port));
> tmp &= BXT_PIPE_SELECT_MASK;
> tmp >>= BXT_PIPE_SELECT_SHIFT;
> @@ -1197,7 +1197,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
>
> pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
>
> - if (IS_GEN9_LP(dev_priv)) {
> + if (GT_GEN9_LP(dev_priv)) {
> bxt_dsi_get_pipe_config(encoder, pipe_config);
> pclk = bxt_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
> pipe_config);
> @@ -1265,7 +1265,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
> hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - if (IS_GEN9_LP(dev_priv)) {
> + if (GT_GEN9_LP(dev_priv)) {
> /*
> * Program hdisplay and vdisplay on MIPI transcoder.
> * This is different from calculated hactive and
> @@ -1352,7 +1352,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> tmp &= ~READ_REQUEST_PRIORITY_MASK;
> I915_WRITE(MIPI_CTRL(port), tmp |
> READ_REQUEST_PRIORITY_HIGH);
> - } else if (IS_GEN9_LP(dev_priv)) {
> + } else if (GT_GEN9_LP(dev_priv)) {
> enum pipe pipe = intel_crtc->pipe;
>
> tmp = I915_READ(MIPI_CTRL(port));
> @@ -1390,7 +1390,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> if (intel_dsi->clock_stop)
> tmp |= CLOCKSTOP;
>
> - if (IS_GEN9_LP(dev_priv)) {
> + if (GT_GEN9_LP(dev_priv)) {
> tmp |= BXT_DPHY_DEFEATURE_EN;
> if (!is_cmd_mode(intel_dsi))
> tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
> @@ -1441,7 +1441,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> I915_WRITE(MIPI_INIT_COUNT(port),
> txclkesc(intel_dsi->escape_clk_div, 100));
>
> - if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
> + if (GT_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
> /*
> * BXT spec says write MIPI_INIT_COUNT for
> * both the ports, even if only one is
> @@ -1520,7 +1520,7 @@ static void intel_dsi_unprepare(struct intel_encoder *encoder)
> /* Panel commands can be sent when clock is in LP11 */
> I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
>
> - if (IS_GEN9_LP(dev_priv))
> + if (GT_GEN9_LP(dev_priv))
> bxt_dsi_reset_clocks(encoder, port);
> else
> vlv_dsi_reset_clocks(encoder, port);
> @@ -1629,7 +1629,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
> if (!intel_bios_is_dsi_present(dev_priv, &port))
> return;
>
> - if (IS_GEN9_LP(dev_priv))
> + if (GT_GEN9_LP(dev_priv))
> dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
> else
> dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
> @@ -1668,7 +1668,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
> * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
> * port C. BXT isn't limited like this.
> */
> - if (IS_GEN9_LP(dev_priv))
> + if (GT_GEN9_LP(dev_priv))
> intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
> else if (port == PORT_A)
> intel_encoder->crtc_mask = BIT(PIPE_A);
> --
> 2.19.1.1.g56c4683e68
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2018-11-21 22:22 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-06 21:51 [PATCH v2 0/7] Make GEN macros more similar Lucas De Marchi
2018-11-06 21:51 ` [PATCH v2 1/7] Revert "drm/i915: Kill GEN_FOREVER" Lucas De Marchi
2018-11-21 22:22 ` Rodrigo Vivi
2018-11-06 21:51 ` [PATCH v2 2/7] drm/i915: Rename IS_GEN to GT_RANGE Lucas De Marchi
2018-11-28 8:02 ` Jani Nikula
2018-11-28 9:27 ` Joonas Lahtinen
2018-11-28 17:04 ` Rodrigo Vivi
2018-11-28 17:34 ` Lucas De Marchi
2018-11-06 21:51 ` [PATCH v2 3/7] drm/i915: replace IS_GEN<N> with GT_GEN(..., N) Lucas De Marchi
2018-11-21 22:20 ` Rodrigo Vivi
2018-11-23 12:42 ` Jani Nikula
2018-11-26 18:49 ` Rodrigo Vivi
2018-11-27 8:31 ` Jani Nikula
2018-11-28 0:09 ` Rodrigo Vivi
2018-11-06 21:51 ` [PATCH v2 4/7] drm/i915: rename IS_GEN9_* to GT_GEN9_* Lucas De Marchi
2018-11-21 22:22 ` Rodrigo Vivi [this message]
2018-11-06 21:51 ` [PATCH v2 5/7] drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE Lucas De Marchi
2018-11-06 21:51 ` [PATCH v2 6/7] drm/i915: merge gen checks to use range Lucas De Marchi
2018-11-21 22:24 ` Rodrigo Vivi
2018-11-06 21:51 ` [PATCH v2 7/7] drm/i915: remove INTEL_GEN macro Lucas De Marchi
2018-11-07 10:05 ` [PATCH v2 0/7] Make GEN macros more similar Tvrtko Ursulin
2018-11-08 0:57 ` Lucas De Marchi
2018-11-08 11:23 ` Tvrtko Ursulin
2018-11-19 22:20 ` Lucas De Marchi
2018-11-20 13:40 ` Tvrtko Ursulin
2018-11-21 22:19 ` Rodrigo Vivi
2018-11-22 8:54 ` Tvrtko Ursulin
2018-11-26 18:46 ` Rodrigo Vivi
2018-11-27 8:37 ` Jani Nikula
2018-11-27 9:36 ` Lucas De Marchi
2018-11-27 11:35 ` Tvrtko Ursulin
2018-11-28 0:19 ` Rodrigo Vivi
2018-11-28 17:22 ` Lucas De Marchi
2018-11-23 12:44 ` Jani Nikula
2018-11-07 14:10 ` ✗ Fi.CI.CHECKPATCH: warning for Make GEN macros more similar (rev2) Patchwork
2018-11-07 14:14 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-07 14:30 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-07 21:17 ` ✓ Fi.CI.IGT: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20181121222256.GI13148@intel.com \
--to=rodrigo.vivi@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=lucas.demarchi@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.