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X-Received-From: 192.55.52.88 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH v5 11/24] hw: acpi: Export and generalize the PCI host AML API X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Zhong , Peter Maydell , Stefano Stabellini , Eduardo Habkost , Rob Bradford , "Michael S. Tsirkin" , qemu-devel@nongnu.org, Shannon Zhao , qemu-arm@nongnu.org, Marcel Apfelbaum , xen-devel@lists.xenproject.org, Anthony Perard , Paolo Bonzini , Richard Henderson Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: 1e/n4q1pp1QH Hi Igor, On Wed, Nov 14, 2018 at 11:55:37AM +0100, Igor Mammedov wrote: > On Mon, 5 Nov 2018 02:40:34 +0100 > Samuel Ortiz wrote: > > > From: Yang Zhong > > > > The AML build routines for the PCI host bridge and the corresponding > > DSDT addition are neither x86 nor PC machine type specific. > > We can move them to the architecture agnostic hw/acpi folder, and by > > carrying all the needed information through a new AcpiPciBus structure, > > we can make them PC machine type independent. > > I'm don't know anything about PCI, but functional changes doesn't look > correct to me. > > See more detailed comments below. > > Marcel, > could you take a look on this patch (in particular main csr changes), pls? > > > > > Signed-off-by: Yang Zhong > > Signed-off-by: Rob Bradford > > Signed-off-by: Samuel Ortiz > > --- > > include/hw/acpi/aml-build.h | 8 ++ > > hw/acpi/aml-build.c | 157 ++++++++++++++++++++++++++++++++++++ > > hw/i386/acpi-build.c | 115 ++------------------------ > > 3 files changed, 173 insertions(+), 107 deletions(-) > > > > diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h > > index fde2785b9a..1861e37ebf 100644 > > --- a/include/hw/acpi/aml-build.h > > +++ b/include/hw/acpi/aml-build.h > > @@ -229,6 +229,12 @@ typedef struct AcpiMcfgInfo { > > uint32_t mcfg_size; > > } AcpiMcfgInfo; > > > > +typedef struct AcpiPciBus { > > + PCIBus *pci_bus; > > + Range *pci_hole; > > + Range *pci_hole64; > > +} AcpiPciBus; > Again, this and all below is not aml-build material. > Consider adding/using pci specific acpi file for it. > > Also even though pci AML in arm/virt is to a large degree a subset > of x86 target and it would be much better to unify ARM part with x86, > it probably will be to big/complex of a change if we take on it in > one go. > > So not to derail you from the goal too much, we probably should > generalize this a little bit less, limiting refactoring to x86 > target for now. So keeping it under i386 means it won't be accessible through hw/acpi/, which means we won't be able to have a generic hw/acpi/reduced.c implementation. From our perspective, this is the problem with keeping things under i386 because we're not sure yet how much generic it is: It still won't be shareable for a generic hardware-reduced ACPI implementation which means we'll have to temporarily have yet another hardware-reduced ACPI implementation under hw/i386 this time. I guess this is what Michael meant by keeping some parts of the code duplicated for now. I feel it'd be easier to move those APIs under a shareable location, to make it easier for ARM to consume it even if it's not entirely generic yet. But you guys are the maintainers and if you think we should restric the generalization to x86 only for now, we can go for it. > For example, move generic x86 pci parts to hw/i386/acpi-pci.[hc], > and structure it so that building blocks in acpi-pci.c could be > reused for x86 reduced profile later. > Once it's been done, it might be easier and less complex to > unify a bit more generic code in i386/acpi-pci.c with corresponding > ARM code. > > Patch is too big and should be split into smaller logical chunks > and you should separate code movement vs functional changes you're > a making here. > > Once you split patch properly, it should be easier to assess > changes. > > > typedef struct CrsRangeEntry { > > uint64_t base; > > uint64_t limit; > > @@ -411,6 +417,8 @@ Aml *build_osc_method(uint32_t value); > > void build_mcfg(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info); > > Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi); > > Aml *build_prt(bool is_pci0_prt); > > +void acpi_dsdt_add_pci_bus(Aml *dsdt, AcpiPciBus *pci_host); > > +Aml *build_pci_host_bridge(Aml *table, AcpiPciBus *pci_host); > > void crs_range_set_init(CrsRangeSet *range_set); > > Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set); > > void crs_replace_with_free_ranges(GPtrArray *ranges, > > diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c > > index b8e32f15f7..869ed70db3 100644 > > --- a/hw/acpi/aml-build.c > > +++ b/hw/acpi/aml-build.c > > @@ -29,6 +29,19 @@ > > #include "hw/pci/pci_bus.h" > > #include "qemu/range.h" > > #include "hw/pci/pci_bridge.h" > > +#include "hw/i386/pc.h" > > +#include "sysemu/tpm.h" > > +#include "hw/acpi/tpm.h" > > + > > +#define PCI_HOST_BRIDGE_CONFIG_ADDR 0xcf8 > > +#define PCI_HOST_BRIDGE_IO_0_MIN_ADDR 0x0000 > > +#define PCI_HOST_BRIDGE_IO_0_MAX_ADDR 0x0cf7 > > +#define PCI_HOST_BRIDGE_IO_1_MIN_ADDR 0x0d00 > > +#define PCI_HOST_BRIDGE_IO_1_MAX_ADDR 0xffff > > +#define PCI_VGA_MEM_BASE_ADDR 0x000a0000 > > +#define PCI_VGA_MEM_MAX_ADDR 0x000bffff > > +#define IO_0_LEN 0xcf8 > > +#define VGA_MEM_LEN 0x20000 > > > > static GArray *build_alloc_array(void) > > { > > @@ -2142,6 +2155,150 @@ Aml *build_prt(bool is_pci0_prt) > > return method; > > } > > > > +Aml *build_pci_host_bridge(Aml *table, AcpiPciBus *pci_host) > name doesn't reflect exactly what function does, > it builds device descriptions for expander buses (including their csr) > and then it builds csr for for main pci host but not pci device description. > > I'd suggest to split out expander buses part into separate function > that returns an expander bus device description, updates crs_range_set > and let the caller to enumerate buses and add descriptions to dsdt. > > Then after it we could do a generic csr generation function for the main pci host > if it's possible at all (main pci host csr seems heavily board depended) > > Instead of taking table and adding stuff directly in to it > it should be cleaner to take as argument empty csr (crs = aml_resource_template();) > add stuff to it and let the caller to add/extend csr as/where necessary. > > > +{ > > + CrsRangeEntry *entry; > > + Aml *scope, *dev, *crs; > > + CrsRangeSet crs_range_set; > > + Range *pci_hole = NULL; > > + Range *pci_hole64 = NULL; > > + PCIBus *bus = NULL; > > + int root_bus_limit = 0xFF; > > + int i; > > + > > + bus = pci_host->pci_bus; > > + assert(bus); > > + pci_hole = pci_host->pci_hole; > > + pci_hole64 = pci_host->pci_hole64; > > + > > + crs_range_set_init(&crs_range_set); > > + QLIST_FOREACH(bus, &bus->child, sibling) { > > + uint8_t bus_num = pci_bus_num(bus); > > + uint8_t numa_node = pci_bus_numa_node(bus); > > + > > + /* look only for expander root buses */ > > + if (!pci_bus_is_root(bus)) { > > + continue; > > + } > > + > > + if (bus_num < root_bus_limit) { > > + root_bus_limit = bus_num - 1; > > + } > > + > > + scope = aml_scope("\\_SB"); > > + dev = aml_device("PC%.02X", bus_num); > > + aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); > > + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); > > + aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); > > + if (pci_bus_is_express(bus)) { > > + aml_append(dev, aml_name_decl("SUPP", aml_int(0))); > > + aml_append(dev, aml_name_decl("CTRL", aml_int(0))); > > + aml_append(dev, build_osc_method(0x1F)); > > + } > > + if (numa_node != NUMA_NODE_UNASSIGNED) { > > + aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); > > + } > > + > > + aml_append(dev, build_prt(false)); > > + crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); > > + aml_append(dev, aml_name_decl("_CRS", crs)); > > + aml_append(scope, dev); > > + aml_append(table, scope); > > + } > > + scope = aml_scope("\\_SB.PCI0"); > > + /* build PCI0._CRS */ > > + crs = aml_resource_template(); > > + /* set the pcie bus num */ > > + aml_append(crs, > > + aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, > > + 0x0000, 0x0, root_bus_limit, > > + 0x0000, root_bus_limit + 1)); > > vvvv > > + aml_append(crs, aml_io(AML_DECODE16, PCI_HOST_BRIDGE_CONFIG_ADDR, > > + PCI_HOST_BRIDGE_CONFIG_ADDR, 0x01, 0x08)); > > + /* set the io region 0 in pci host bridge */ > > + aml_append(crs, > > + aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, > > + AML_POS_DECODE, AML_ENTIRE_RANGE, > > + 0x0000, PCI_HOST_BRIDGE_IO_0_MIN_ADDR, > > + PCI_HOST_BRIDGE_IO_0_MAX_ADDR, 0x0000, IO_0_LEN)); > > + > > + /* set the io region 1 in pci host bridge */ > > + crs_replace_with_free_ranges(crs_range_set.io_ranges, > > + PCI_HOST_BRIDGE_IO_1_MIN_ADDR, > > + PCI_HOST_BRIDGE_IO_1_MAX_ADDR); > above code doesn't look as just a movement, it's something totally new, > so it should be in it's own patch with a justification why it's ok > to replace concrete addresses with some kind of window. Ah I see your point now. Yes, I agree this should be in a separate patch. Cheers, Samuel. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Samuel Ortiz Subject: Re: [Qemu-devel] [PATCH v5 11/24] hw: acpi: Export and generalize the PCI host AML API Date: Thu, 22 Nov 2018 00:12:17 +0100 Message-ID: <20181121231217.GA4450@caravaggio> References: <20181105014047.26447-1-sameo@linux.intel.com> <20181105014047.26447-12-sameo@linux.intel.com> <20181114115537.3357921b@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gPbg2-0005og-Jo for xen-devel@lists.xenproject.org; Wed, 21 Nov 2018 23:12:58 +0000 Content-Disposition: inline In-Reply-To: <20181114115537.3357921b@redhat.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To: Igor Mammedov Cc: Yang Zhong , Peter Maydell , Stefano Stabellini , Eduardo Habkost , Rob Bradford , "Michael S. Tsirkin" , qemu-devel@nongnu.org, Shannon Zhao , qemu-arm@nongnu.org, Marcel Apfelbaum , xen-devel@lists.xenproject.org, Anthony Perard , Paolo Bonzini , Richard Henderson List-Id: xen-devel@lists.xenproject.org SGkgSWdvciwKCk9uIFdlZCwgTm92IDE0LCAyMDE4IGF0IDExOjU1OjM3QU0gKzAxMDAsIElnb3Ig TWFtbWVkb3Ygd3JvdGU6Cj4gT24gTW9uLCAgNSBOb3YgMjAxOCAwMjo0MDozNCArMDEwMAo+IFNh bXVlbCBPcnRpeiA8c2FtZW9AbGludXguaW50ZWwuY29tPiB3cm90ZToKPiAKPiA+IEZyb206IFlh bmcgWmhvbmcgPHlhbmcuemhvbmdAaW50ZWwuY29tPgo+ID4gCj4gPiBUaGUgQU1MIGJ1aWxkIHJv dXRpbmVzIGZvciB0aGUgUENJIGhvc3QgYnJpZGdlIGFuZCB0aGUgY29ycmVzcG9uZGluZwo+ID4g RFNEVCBhZGRpdGlvbiBhcmUgbmVpdGhlciB4ODYgbm9yIFBDIG1hY2hpbmUgdHlwZSBzcGVjaWZp Yy4KPiA+IFdlIGNhbiBtb3ZlIHRoZW0gdG8gdGhlIGFyY2hpdGVjdHVyZSBhZ25vc3RpYyBody9h Y3BpIGZvbGRlciwgYW5kIGJ5Cj4gPiBjYXJyeWluZyBhbGwgdGhlIG5lZWRlZCBpbmZvcm1hdGlv biB0aHJvdWdoIGEgbmV3IEFjcGlQY2lCdXMgc3RydWN0dXJlLAo+ID4gd2UgY2FuIG1ha2UgdGhl bSBQQyBtYWNoaW5lIHR5cGUgaW5kZXBlbmRlbnQuCj4gCj4gSSdtIGRvbid0IGtub3cgYW55dGhp bmcgYWJvdXQgUENJLCBidXQgZnVuY3Rpb25hbCBjaGFuZ2VzIGRvZXNuJ3QgbG9vawo+IGNvcnJl Y3QgdG8gbWUuCj4KPiBTZWUgbW9yZSBkZXRhaWxlZCBjb21tZW50cyBiZWxvdy4KPiAKPiBNYXJj ZWwsCj4gY291bGQgeW91IHRha2UgYSBsb29rIG9uIHRoaXMgcGF0Y2ggKGluIHBhcnRpY3VsYXIg bWFpbiBjc3IgY2hhbmdlcyksIHBscz8KPiAKPiA+IAo+ID4gU2lnbmVkLW9mZi1ieTogWWFuZyBa aG9uZyA8eWFuZy56aG9uZ0BpbnRlbC5jb20+Cj4gPiBTaWduZWQtb2ZmLWJ5OiBSb2IgQnJhZGZv cmQgPHJvYmVydC5icmFkZm9yZEBpbnRlbC5jb20+Cj4gPiBTaWduZWQtb2ZmLWJ5OiBTYW11ZWwg T3J0aXogPHNhbWVvQGxpbnV4LmludGVsLmNvbT4KPiA+IC0tLQo+ID4gIGluY2x1ZGUvaHcvYWNw aS9hbWwtYnVpbGQuaCB8ICAgOCArKwo+ID4gIGh3L2FjcGkvYW1sLWJ1aWxkLmMgICAgICAgICB8 IDE1NyArKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysKPiA+ICBody9pMzg2L2Fj cGktYnVpbGQuYyAgICAgICAgfCAxMTUgKystLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0KPiA+ICAz IGZpbGVzIGNoYW5nZWQsIDE3MyBpbnNlcnRpb25zKCspLCAxMDcgZGVsZXRpb25zKC0pCj4gPiAK PiA+IGRpZmYgLS1naXQgYS9pbmNsdWRlL2h3L2FjcGkvYW1sLWJ1aWxkLmggYi9pbmNsdWRlL2h3 L2FjcGkvYW1sLWJ1aWxkLmgKPiA+IGluZGV4IGZkZTI3ODViOWEuLjE4NjFlMzdlYmYgMTAwNjQ0 Cj4gPiAtLS0gYS9pbmNsdWRlL2h3L2FjcGkvYW1sLWJ1aWxkLmgKPiA+ICsrKyBiL2luY2x1ZGUv aHcvYWNwaS9hbWwtYnVpbGQuaAo+ID4gQEAgLTIyOSw2ICsyMjksMTIgQEAgdHlwZWRlZiBzdHJ1 Y3QgQWNwaU1jZmdJbmZvIHsKPiA+ICAgICAgdWludDMyX3QgbWNmZ19zaXplOwo+ID4gIH0gQWNw aU1jZmdJbmZvOwo+ID4gIAo+ID4gK3R5cGVkZWYgc3RydWN0IEFjcGlQY2lCdXMgewo+ID4gKyAg ICBQQ0lCdXMgKnBjaV9idXM7Cj4gPiArICAgIFJhbmdlICpwY2lfaG9sZTsKPiA+ICsgICAgUmFu Z2UgKnBjaV9ob2xlNjQ7Cj4gPiArfSBBY3BpUGNpQnVzOwo+IEFnYWluLCB0aGlzIGFuZCBhbGwg YmVsb3cgaXMgbm90IGFtbC1idWlsZCBtYXRlcmlhbC4KPiBDb25zaWRlciBhZGRpbmcvdXNpbmcg cGNpIHNwZWNpZmljIGFjcGkgZmlsZSBmb3IgaXQuCj4gCj4gQWxzbyBldmVuIHRob3VnaCBwY2kg QU1MIGluIGFybS92aXJ0IGlzIHRvIGEgbGFyZ2UgZGVncmVlIGEgc3Vic2V0Cj4gb2YgeDg2IHRh cmdldCBhbmQgaXQgd291bGQgYmUgbXVjaCBiZXR0ZXIgdG8gdW5pZnkgQVJNIHBhcnQgd2l0aCB4 ODYsCj4gaXQgcHJvYmFibHkgd2lsbCBiZSB0byBiaWcvY29tcGxleCBvZiBhIGNoYW5nZSBpZiB3 ZSB0YWtlIG9uIGl0IGluCj4gb25lIGdvLgo+IAo+IFNvIG5vdCB0byBkZXJhaWwgeW91IGZyb20g dGhlIGdvYWwgdG9vIG11Y2gsIHdlIHByb2JhYmx5IHNob3VsZAo+IGdlbmVyYWxpemUgdGhpcyBh IGxpdHRsZSBiaXQgbGVzcywgbGltaXRpbmcgcmVmYWN0b3JpbmcgdG8geDg2Cj4gdGFyZ2V0IGZv ciBub3cuClNvIGtlZXBpbmcgaXQgdW5kZXIgaTM4NiBtZWFucyBpdCB3b24ndCBiZSBhY2Nlc3Np YmxlIHRocm91Z2ggaHcvYWNwaS8sCndoaWNoIG1lYW5zIHdlIHdvbid0IGJlIGFibGUgdG8gaGF2 ZSBhIGdlbmVyaWMgaHcvYWNwaS9yZWR1Y2VkLmMKaW1wbGVtZW50YXRpb24uIEZyb20gb3VyIHBl cnNwZWN0aXZlLCB0aGlzIGlzIHRoZSBwcm9ibGVtIHdpdGgga2VlcGluZwp0aGluZ3MgdW5kZXIg aTM4NiBiZWNhdXNlIHdlJ3JlIG5vdCBzdXJlIHlldCBob3cgbXVjaCBnZW5lcmljIGl0IGlzOiBJ dApzdGlsbCB3b24ndCBiZSBzaGFyZWFibGUgZm9yIGEgZ2VuZXJpYyBoYXJkd2FyZS1yZWR1Y2Vk IEFDUEkKaW1wbGVtZW50YXRpb24gd2hpY2ggbWVhbnMgd2UnbGwgaGF2ZSB0byB0ZW1wb3Jhcmls eSBoYXZlIHlldCBhbm90aGVyCmhhcmR3YXJlLXJlZHVjZWQgQUNQSSBpbXBsZW1lbnRhdGlvbiB1 bmRlciBody9pMzg2IHRoaXMgdGltZS4KSSBndWVzcyB0aGlzIGlzIHdoYXQgTWljaGFlbCBtZWFu dCBieSBrZWVwaW5nIHNvbWUgcGFydHMgb2YgdGhlIGNvZGUKZHVwbGljYXRlZCBmb3Igbm93LgoK SSBmZWVsIGl0J2QgYmUgZWFzaWVyIHRvIG1vdmUgdGhvc2UgQVBJcyB1bmRlciBhIHNoYXJlYWJs ZSBsb2NhdGlvbiwgdG8KbWFrZSBpdCBlYXNpZXIgZm9yIEFSTSB0byBjb25zdW1lIGl0IGV2ZW4g aWYgaXQncyBub3QgZW50aXJlbHkgZ2VuZXJpYyB5ZXQuCkJ1dCB5b3UgZ3V5cyBhcmUgdGhlIG1h aW50YWluZXJzIGFuZCBpZiB5b3UgdGhpbmsgd2Ugc2hvdWxkIHJlc3RyaWMgdGhlCmdlbmVyYWxp emF0aW9uIHRvIHg4NiBvbmx5IGZvciBub3csIHdlIGNhbiBnbyBmb3IgaXQuCgo+IEZvciBleGFt cGxlLCBtb3ZlIGdlbmVyaWMgeDg2IHBjaSBwYXJ0cyB0byBody9pMzg2L2FjcGktcGNpLltoY10s Cj4gYW5kIHN0cnVjdHVyZSBpdCBzbyB0aGF0IGJ1aWxkaW5nIGJsb2NrcyBpbiBhY3BpLXBjaS5j IGNvdWxkIGJlCj4gcmV1c2VkIGZvciB4ODYgcmVkdWNlZCBwcm9maWxlIGxhdGVyLgo+IE9uY2Ug aXQncyBiZWVuIGRvbmUsIGl0IG1pZ2h0IGJlIGVhc2llciBhbmQgbGVzcyBjb21wbGV4IHRvCj4g dW5pZnkgYSBiaXQgbW9yZSBnZW5lcmljIGNvZGUgaW4gaTM4Ni9hY3BpLXBjaS5jIHdpdGggY29y cmVzcG9uZGluZwo+IEFSTSBjb2RlLgo+IAo+IFBhdGNoIGlzIHRvbyBiaWcgYW5kIHNob3VsZCBi ZSBzcGxpdCBpbnRvIHNtYWxsZXIgbG9naWNhbCBjaHVua3MKPiBhbmQgeW91IHNob3VsZCBzZXBh cmF0ZSBjb2RlIG1vdmVtZW50IHZzIGZ1bmN0aW9uYWwgY2hhbmdlcyB5b3UncmUKPiBhIG1ha2lu ZyBoZXJlLgo+IAo+IE9uY2UgeW91IHNwbGl0IHBhdGNoIHByb3Blcmx5LCBpdCBzaG91bGQgYmUg ZWFzaWVyIHRvIGFzc2Vzcwo+IGNoYW5nZXMuCj4gCj4gPiAgdHlwZWRlZiBzdHJ1Y3QgQ3JzUmFu Z2VFbnRyeSB7Cj4gPiAgICAgIHVpbnQ2NF90IGJhc2U7Cj4gPiAgICAgIHVpbnQ2NF90IGxpbWl0 Owo+ID4gQEAgLTQxMSw2ICs0MTcsOCBAQCBBbWwgKmJ1aWxkX29zY19tZXRob2QodWludDMyX3Qg dmFsdWUpOwo+ID4gIHZvaWQgYnVpbGRfbWNmZyhHQXJyYXkgKnRhYmxlX2RhdGEsIEJJT1NMaW5r ZXIgKmxpbmtlciwgQWNwaU1jZmdJbmZvICppbmZvKTsKPiA+ICBBbWwgKmJ1aWxkX2dzaV9saW5r X2Rldihjb25zdCBjaGFyICpuYW1lLCB1aW50OF90IHVpZCwgdWludDhfdCBnc2kpOwo+ID4gIEFt bCAqYnVpbGRfcHJ0KGJvb2wgaXNfcGNpMF9wcnQpOwo+ID4gK3ZvaWQgYWNwaV9kc2R0X2FkZF9w Y2lfYnVzKEFtbCAqZHNkdCwgQWNwaVBjaUJ1cyAqcGNpX2hvc3QpOwo+ID4gK0FtbCAqYnVpbGRf cGNpX2hvc3RfYnJpZGdlKEFtbCAqdGFibGUsIEFjcGlQY2lCdXMgKnBjaV9ob3N0KTsKPiA+ICB2 b2lkIGNyc19yYW5nZV9zZXRfaW5pdChDcnNSYW5nZVNldCAqcmFuZ2Vfc2V0KTsKPiA+ICBBbWwg KmJ1aWxkX2NycyhQQ0lIb3N0U3RhdGUgKmhvc3QsIENyc1JhbmdlU2V0ICpyYW5nZV9zZXQpOwo+ ID4gIHZvaWQgY3JzX3JlcGxhY2Vfd2l0aF9mcmVlX3JhbmdlcyhHUHRyQXJyYXkgKnJhbmdlcywK PiA+IGRpZmYgLS1naXQgYS9ody9hY3BpL2FtbC1idWlsZC5jIGIvaHcvYWNwaS9hbWwtYnVpbGQu Ywo+ID4gaW5kZXggYjhlMzJmMTVmNy4uODY5ZWQ3MGRiMyAxMDA2NDQKPiA+IC0tLSBhL2h3L2Fj cGkvYW1sLWJ1aWxkLmMKPiA+ICsrKyBiL2h3L2FjcGkvYW1sLWJ1aWxkLmMKPiA+IEBAIC0yOSw2 ICsyOSwxOSBAQAo+ID4gICNpbmNsdWRlICJody9wY2kvcGNpX2J1cy5oIgo+ID4gICNpbmNsdWRl ICJxZW11L3JhbmdlLmgiCj4gPiAgI2luY2x1ZGUgImh3L3BjaS9wY2lfYnJpZGdlLmgiCj4gPiAr I2luY2x1ZGUgImh3L2kzODYvcGMuaCIKPiA+ICsjaW5jbHVkZSAic3lzZW11L3RwbS5oIgo+ID4g KyNpbmNsdWRlICJody9hY3BpL3RwbS5oIgo+ID4gKwo+ID4gKyNkZWZpbmUgUENJX0hPU1RfQlJJ REdFX0NPTkZJR19BRERSICAgICAgICAweGNmOAo+ID4gKyNkZWZpbmUgUENJX0hPU1RfQlJJREdF X0lPXzBfTUlOX0FERFIgICAgICAweDAwMDAKPiA+ICsjZGVmaW5lIFBDSV9IT1NUX0JSSURHRV9J T18wX01BWF9BRERSICAgICAgMHgwY2Y3Cj4gPiArI2RlZmluZSBQQ0lfSE9TVF9CUklER0VfSU9f MV9NSU5fQUREUiAgICAgIDB4MGQwMAo+ID4gKyNkZWZpbmUgUENJX0hPU1RfQlJJREdFX0lPXzFf TUFYX0FERFIgICAgICAweGZmZmYKPiA+ICsjZGVmaW5lIFBDSV9WR0FfTUVNX0JBU0VfQUREUiAg ICAgICAgICAgICAgMHgwMDBhMDAwMAo+ID4gKyNkZWZpbmUgUENJX1ZHQV9NRU1fTUFYX0FERFIg ICAgICAgICAgICAgICAweDAwMGJmZmZmCj4gPiArI2RlZmluZSBJT18wX0xFTiAgICAgICAgICAg ICAgICAgICAgICAgICAgIDB4Y2Y4Cj4gPiArI2RlZmluZSBWR0FfTUVNX0xFTiAgICAgICAgICAg ICAgICAgICAgICAgIDB4MjAwMDAKPiA+ICAKPiA+ICBzdGF0aWMgR0FycmF5ICpidWlsZF9hbGxv Y19hcnJheSh2b2lkKQo+ID4gIHsKPiA+IEBAIC0yMTQyLDYgKzIxNTUsMTUwIEBAIEFtbCAqYnVp bGRfcHJ0KGJvb2wgaXNfcGNpMF9wcnQpCj4gPiAgICAgIHJldHVybiBtZXRob2Q7Cj4gPiAgfQo+ ID4gIAo+ID4gK0FtbCAqYnVpbGRfcGNpX2hvc3RfYnJpZGdlKEFtbCAqdGFibGUsIEFjcGlQY2lC dXMgKnBjaV9ob3N0KQo+IG5hbWUgZG9lc24ndCByZWZsZWN0IGV4YWN0bHkgd2hhdCBmdW5jdGlv biBkb2VzLAo+IGl0IGJ1aWxkcyBkZXZpY2UgZGVzY3JpcHRpb25zIGZvciBleHBhbmRlciBidXNl cyAoaW5jbHVkaW5nIHRoZWlyIGNzcikKPiBhbmQgdGhlbiBpdCBidWlsZHMgY3NyIGZvciBmb3Ig bWFpbiBwY2kgaG9zdCBidXQgbm90IHBjaSBkZXZpY2UgZGVzY3JpcHRpb24uCj4gCj4gSSdkIHN1 Z2dlc3QgdG8gc3BsaXQgb3V0IGV4cGFuZGVyIGJ1c2VzIHBhcnQgaW50byBzZXBhcmF0ZSBmdW5j dGlvbgo+IHRoYXQgcmV0dXJucyBhbiBleHBhbmRlciBidXMgZGV2aWNlIGRlc2NyaXB0aW9uLCB1 cGRhdGVzIGNyc19yYW5nZV9zZXQKPiBhbmQgbGV0IHRoZSBjYWxsZXIgdG8gZW51bWVyYXRlIGJ1 c2VzIGFuZCBhZGQgZGVzY3JpcHRpb25zIHRvIGRzZHQuCj4gCj4gVGhlbiBhZnRlciBpdCB3ZSBj b3VsZCBkbyBhIGdlbmVyaWMgY3NyIGdlbmVyYXRpb24gZnVuY3Rpb24gZm9yIHRoZSBtYWluIHBj aSBob3N0Cj4gaWYgaXQncyBwb3NzaWJsZSBhdCBhbGwgKG1haW4gcGNpIGhvc3QgY3NyIHNlZW1z IGhlYXZpbHkgYm9hcmQgZGVwZW5kZWQpCj4gCj4gSW5zdGVhZCBvZiB0YWtpbmcgdGFibGUgYW5k IGFkZGluZyBzdHVmZiBkaXJlY3RseSBpbiB0byBpdAo+IGl0IHNob3VsZCBiZSBjbGVhbmVyIHRv IHRha2UgYXMgYXJndW1lbnQgZW1wdHkgY3NyIChjcnMgPSBhbWxfcmVzb3VyY2VfdGVtcGxhdGUo KTspCj4gYWRkIHN0dWZmIHRvIGl0IGFuZCBsZXQgdGhlIGNhbGxlciB0byBhZGQvZXh0ZW5kIGNz ciBhcy93aGVyZSBuZWNlc3NhcnkuCj4gCj4gPiArewo+ID4gKyAgICBDcnNSYW5nZUVudHJ5ICpl bnRyeTsKPiA+ICsgICAgQW1sICpzY29wZSwgKmRldiwgKmNyczsKPiA+ICsgICAgQ3JzUmFuZ2VT ZXQgY3JzX3JhbmdlX3NldDsKPiA+ICsgICAgUmFuZ2UgKnBjaV9ob2xlID0gTlVMTDsKPiA+ICsg ICAgUmFuZ2UgKnBjaV9ob2xlNjQgPSBOVUxMOwo+ID4gKyAgICBQQ0lCdXMgKmJ1cyA9IE5VTEw7 Cj4gPiArICAgIGludCByb290X2J1c19saW1pdCA9IDB4RkY7Cj4gPiArICAgIGludCBpOwo+ID4g Kwo+ID4gKyAgICBidXMgPSBwY2lfaG9zdC0+cGNpX2J1czsKPiA+ICsgICAgYXNzZXJ0KGJ1cyk7 Cj4gPiArICAgIHBjaV9ob2xlID0gcGNpX2hvc3QtPnBjaV9ob2xlOwo+ID4gKyAgICBwY2lfaG9s ZTY0ID0gcGNpX2hvc3QtPnBjaV9ob2xlNjQ7Cj4gPiArCj4gPiArICAgIGNyc19yYW5nZV9zZXRf aW5pdCgmY3JzX3JhbmdlX3NldCk7Cj4gPiArICAgIFFMSVNUX0ZPUkVBQ0goYnVzLCAmYnVzLT5j aGlsZCwgc2libGluZykgewo+ID4gKyAgICAgICAgdWludDhfdCBidXNfbnVtID0gcGNpX2J1c19u dW0oYnVzKTsKPiA+ICsgICAgICAgIHVpbnQ4X3QgbnVtYV9ub2RlID0gcGNpX2J1c19udW1hX25v ZGUoYnVzKTsKPiA+ICsKPiA+ICsgICAgICAgIC8qIGxvb2sgb25seSBmb3IgZXhwYW5kZXIgcm9v dCBidXNlcyAqLwo+ID4gKyAgICAgICAgaWYgKCFwY2lfYnVzX2lzX3Jvb3QoYnVzKSkgewo+ID4g KyAgICAgICAgICAgIGNvbnRpbnVlOwo+ID4gKyAgICAgICAgfQo+ID4gKwo+ID4gKyAgICAgICAg aWYgKGJ1c19udW0gPCByb290X2J1c19saW1pdCkgewo+ID4gKyAgICAgICAgICAgIHJvb3RfYnVz X2xpbWl0ID0gYnVzX251bSAtIDE7Cj4gPiArICAgICAgICB9Cj4gPiArCj4gPiArICAgICAgICBz Y29wZSA9IGFtbF9zY29wZSgiXFxfU0IiKTsKPiA+ICsgICAgICAgIGRldiA9IGFtbF9kZXZpY2Uo IlBDJS4wMlgiLCBidXNfbnVtKTsKPiA+ICsgICAgICAgIGFtbF9hcHBlbmQoZGV2LCBhbWxfbmFt ZV9kZWNsKCJfVUlEIiwgYW1sX2ludChidXNfbnVtKSkpOwo+ID4gKyAgICAgICAgYW1sX2FwcGVu ZChkZXYsIGFtbF9uYW1lX2RlY2woIl9ISUQiLCBhbWxfZWlzYWlkKCJQTlAwQTAzIikpKTsKPiA+ ICsgICAgICAgIGFtbF9hcHBlbmQoZGV2LCBhbWxfbmFtZV9kZWNsKCJfQkJOIiwgYW1sX2ludChi dXNfbnVtKSkpOwo+ID4gKyAgICAgICAgaWYgKHBjaV9idXNfaXNfZXhwcmVzcyhidXMpKSB7Cj4g PiArICAgICAgICAgICAgYW1sX2FwcGVuZChkZXYsIGFtbF9uYW1lX2RlY2woIlNVUFAiLCBhbWxf aW50KDApKSk7Cj4gPiArICAgICAgICAgICAgYW1sX2FwcGVuZChkZXYsIGFtbF9uYW1lX2RlY2wo IkNUUkwiLCBhbWxfaW50KDApKSk7Cj4gPiArICAgICAgICAgICAgYW1sX2FwcGVuZChkZXYsIGJ1 aWxkX29zY19tZXRob2QoMHgxRikpOwo+ID4gKyAgICAgICAgfQo+ID4gKyAgICAgICAgaWYgKG51 bWFfbm9kZSAhPSBOVU1BX05PREVfVU5BU1NJR05FRCkgewo+ID4gKyAgICAgICAgICAgIGFtbF9h cHBlbmQoZGV2LCBhbWxfbmFtZV9kZWNsKCJfUFhNIiwgYW1sX2ludChudW1hX25vZGUpKSk7Cj4g PiArICAgICAgICB9Cj4gPiArCj4gPiArICAgICAgICBhbWxfYXBwZW5kKGRldiwgYnVpbGRfcHJ0 KGZhbHNlKSk7Cj4gPiArICAgICAgICBjcnMgPSBidWlsZF9jcnMoUENJX0hPU1RfQlJJREdFKEJV UyhidXMpLT5wYXJlbnQpLCAmY3JzX3JhbmdlX3NldCk7Cj4gPiArICAgICAgICBhbWxfYXBwZW5k KGRldiwgYW1sX25hbWVfZGVjbCgiX0NSUyIsIGNycykpOwo+ID4gKyAgICAgICAgYW1sX2FwcGVu ZChzY29wZSwgZGV2KTsKPiA+ICsgICAgICAgIGFtbF9hcHBlbmQodGFibGUsIHNjb3BlKTsKPiA+ ICsgICAgfQo+ID4gKyAgICBzY29wZSA9IGFtbF9zY29wZSgiXFxfU0IuUENJMCIpOwo+ID4gKyAg ICAvKiBidWlsZCBQQ0kwLl9DUlMgKi8KPiA+ICsgICAgY3JzID0gYW1sX3Jlc291cmNlX3RlbXBs YXRlKCk7Cj4gPiArICAgIC8qIHNldCB0aGUgcGNpZSBidXMgbnVtICovCj4gPiArICAgIGFtbF9h cHBlbmQoY3JzLAo+ID4gKyAgICAgICAgYW1sX3dvcmRfYnVzX251bWJlcihBTUxfTUlOX0ZJWEVE LCBBTUxfTUFYX0ZJWEVELCBBTUxfUE9TX0RFQ09ERSwKPiA+ICsgICAgICAgICAgICAgICAgICAg ICAgICAgICAgMHgwMDAwLCAweDAsIHJvb3RfYnVzX2xpbWl0LAo+ID4gKyAgICAgICAgICAgICAg ICAgICAgICAgICAgICAweDAwMDAsIHJvb3RfYnVzX2xpbWl0ICsgMSkpOwo+IAo+IHZ2dnYKPiA+ ICsgICAgYW1sX2FwcGVuZChjcnMsIGFtbF9pbyhBTUxfREVDT0RFMTYsIFBDSV9IT1NUX0JSSURH RV9DT05GSUdfQUREUiwKPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICBQQ0lfSE9TVF9C UklER0VfQ09ORklHX0FERFIsIDB4MDEsIDB4MDgpKTsKPiA+ICsgICAgLyogc2V0IHRoZSBpbyBy ZWdpb24gMCBpbiBwY2kgaG9zdCBicmlkZ2UgKi8KPiA+ICsgICAgYW1sX2FwcGVuZChjcnMsCj4g PiArICAgICAgICBhbWxfd29yZF9pbyhBTUxfTUlOX0ZJWEVELCBBTUxfTUFYX0ZJWEVELAo+ID4g KyAgICAgICAgICAgICAgICAgICAgQU1MX1BPU19ERUNPREUsIEFNTF9FTlRJUkVfUkFOR0UsCj4g PiArICAgICAgICAgICAgICAgICAgICAweDAwMDAsIFBDSV9IT1NUX0JSSURHRV9JT18wX01JTl9B RERSLAo+ID4gKyAgICAgICAgICAgICAgICAgICAgUENJX0hPU1RfQlJJREdFX0lPXzBfTUFYX0FE RFIsIDB4MDAwMCwgSU9fMF9MRU4pKTsKPiA+ICsKPiA+ICsgICAgLyogc2V0IHRoZSBpbyByZWdp b24gMSBpbiBwY2kgaG9zdCBicmlkZ2UgKi8KPiA+ICsgICAgY3JzX3JlcGxhY2Vfd2l0aF9mcmVl X3JhbmdlcyhjcnNfcmFuZ2Vfc2V0LmlvX3JhbmdlcywKPiA+ICsgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICBQQ0lfSE9TVF9CUklER0VfSU9fMV9NSU5fQUREUiwKPiA+ICsgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICBQQ0lfSE9TVF9CUklER0VfSU9fMV9NQVhfQUREUik7 Cj4gYWJvdmUgY29kZSBkb2Vzbid0IGxvb2sgYXMganVzdCBhIG1vdmVtZW50LCBpdCdzIHNvbWV0 aGluZyB0b3RhbGx5IG5ldywKPiBzbyBpdCBzaG91bGQgYmUgaW4gaXQncyBvd24gcGF0Y2ggd2l0 aCBhIGp1c3RpZmljYXRpb24gd2h5IGl0J3Mgb2sKPiB0byByZXBsYWNlIGNvbmNyZXRlIGFkZHJl c3NlcyB3aXRoIHNvbWUga2luZCBvZiB3aW5kb3cuCkFoIEkgc2VlIHlvdXIgcG9pbnQgbm93LiBZ ZXMsIEkgYWdyZWUgdGhpcyBzaG91bGQgYmUgaW4gYSBzZXBhcmF0ZQpwYXRjaC4KCkNoZWVycywK U2FtdWVsLgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18K WGVuLWRldmVsIG1haWxpbmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVucHJvamVjdC5vcmcKaHR0 cHM6Ly9saXN0cy54ZW5wcm9qZWN0Lm9yZy9tYWlsbWFuL2xpc3RpbmZvL3hlbi1kZXZlbA== From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41134) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gPbgD-0001vU-FK for qemu-devel@nongnu.org; Wed, 21 Nov 2018 18:13:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gPbgC-00027y-1s for qemu-devel@nongnu.org; Wed, 21 Nov 2018 18:13:09 -0500 Date: Thu, 22 Nov 2018 00:12:17 +0100 From: Samuel Ortiz Message-ID: <20181121231217.GA4450@caravaggio> References: <20181105014047.26447-1-sameo@linux.intel.com> <20181105014047.26447-12-sameo@linux.intel.com> <20181114115537.3357921b@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20181114115537.3357921b@redhat.com> Subject: Re: [Qemu-devel] [PATCH v5 11/24] hw: acpi: Export and generalize the PCI host AML API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Igor Mammedov Cc: Marcel Apfelbaum , Yang Zhong , Peter Maydell , Stefano Stabellini , Eduardo Habkost , Rob Bradford , "Michael S. Tsirkin" , qemu-devel@nongnu.org, Shannon Zhao , qemu-arm@nongnu.org, Paolo Bonzini , Anthony Perard , xen-devel@lists.xenproject.org, Richard Henderson Hi Igor, On Wed, Nov 14, 2018 at 11:55:37AM +0100, Igor Mammedov wrote: > On Mon, 5 Nov 2018 02:40:34 +0100 > Samuel Ortiz wrote: > > > From: Yang Zhong > > > > The AML build routines for the PCI host bridge and the corresponding > > DSDT addition are neither x86 nor PC machine type specific. > > We can move them to the architecture agnostic hw/acpi folder, and by > > carrying all the needed information through a new AcpiPciBus structure, > > we can make them PC machine type independent. > > I'm don't know anything about PCI, but functional changes doesn't look > correct to me. > > See more detailed comments below. > > Marcel, > could you take a look on this patch (in particular main csr changes), pls? > > > > > Signed-off-by: Yang Zhong > > Signed-off-by: Rob Bradford > > Signed-off-by: Samuel Ortiz > > --- > > include/hw/acpi/aml-build.h | 8 ++ > > hw/acpi/aml-build.c | 157 ++++++++++++++++++++++++++++++++++++ > > hw/i386/acpi-build.c | 115 ++------------------------ > > 3 files changed, 173 insertions(+), 107 deletions(-) > > > > diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h > > index fde2785b9a..1861e37ebf 100644 > > --- a/include/hw/acpi/aml-build.h > > +++ b/include/hw/acpi/aml-build.h > > @@ -229,6 +229,12 @@ typedef struct AcpiMcfgInfo { > > uint32_t mcfg_size; > > } AcpiMcfgInfo; > > > > +typedef struct AcpiPciBus { > > + PCIBus *pci_bus; > > + Range *pci_hole; > > + Range *pci_hole64; > > +} AcpiPciBus; > Again, this and all below is not aml-build material. > Consider adding/using pci specific acpi file for it. > > Also even though pci AML in arm/virt is to a large degree a subset > of x86 target and it would be much better to unify ARM part with x86, > it probably will be to big/complex of a change if we take on it in > one go. > > So not to derail you from the goal too much, we probably should > generalize this a little bit less, limiting refactoring to x86 > target for now. So keeping it under i386 means it won't be accessible through hw/acpi/, which means we won't be able to have a generic hw/acpi/reduced.c implementation. From our perspective, this is the problem with keeping things under i386 because we're not sure yet how much generic it is: It still won't be shareable for a generic hardware-reduced ACPI implementation which means we'll have to temporarily have yet another hardware-reduced ACPI implementation under hw/i386 this time. I guess this is what Michael meant by keeping some parts of the code duplicated for now. I feel it'd be easier to move those APIs under a shareable location, to make it easier for ARM to consume it even if it's not entirely generic yet. But you guys are the maintainers and if you think we should restric the generalization to x86 only for now, we can go for it. > For example, move generic x86 pci parts to hw/i386/acpi-pci.[hc], > and structure it so that building blocks in acpi-pci.c could be > reused for x86 reduced profile later. > Once it's been done, it might be easier and less complex to > unify a bit more generic code in i386/acpi-pci.c with corresponding > ARM code. > > Patch is too big and should be split into smaller logical chunks > and you should separate code movement vs functional changes you're > a making here. > > Once you split patch properly, it should be easier to assess > changes. > > > typedef struct CrsRangeEntry { > > uint64_t base; > > uint64_t limit; > > @@ -411,6 +417,8 @@ Aml *build_osc_method(uint32_t value); > > void build_mcfg(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info); > > Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi); > > Aml *build_prt(bool is_pci0_prt); > > +void acpi_dsdt_add_pci_bus(Aml *dsdt, AcpiPciBus *pci_host); > > +Aml *build_pci_host_bridge(Aml *table, AcpiPciBus *pci_host); > > void crs_range_set_init(CrsRangeSet *range_set); > > Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set); > > void crs_replace_with_free_ranges(GPtrArray *ranges, > > diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c > > index b8e32f15f7..869ed70db3 100644 > > --- a/hw/acpi/aml-build.c > > +++ b/hw/acpi/aml-build.c > > @@ -29,6 +29,19 @@ > > #include "hw/pci/pci_bus.h" > > #include "qemu/range.h" > > #include "hw/pci/pci_bridge.h" > > +#include "hw/i386/pc.h" > > +#include "sysemu/tpm.h" > > +#include "hw/acpi/tpm.h" > > + > > +#define PCI_HOST_BRIDGE_CONFIG_ADDR 0xcf8 > > +#define PCI_HOST_BRIDGE_IO_0_MIN_ADDR 0x0000 > > +#define PCI_HOST_BRIDGE_IO_0_MAX_ADDR 0x0cf7 > > +#define PCI_HOST_BRIDGE_IO_1_MIN_ADDR 0x0d00 > > +#define PCI_HOST_BRIDGE_IO_1_MAX_ADDR 0xffff > > +#define PCI_VGA_MEM_BASE_ADDR 0x000a0000 > > +#define PCI_VGA_MEM_MAX_ADDR 0x000bffff > > +#define IO_0_LEN 0xcf8 > > +#define VGA_MEM_LEN 0x20000 > > > > static GArray *build_alloc_array(void) > > { > > @@ -2142,6 +2155,150 @@ Aml *build_prt(bool is_pci0_prt) > > return method; > > } > > > > +Aml *build_pci_host_bridge(Aml *table, AcpiPciBus *pci_host) > name doesn't reflect exactly what function does, > it builds device descriptions for expander buses (including their csr) > and then it builds csr for for main pci host but not pci device description. > > I'd suggest to split out expander buses part into separate function > that returns an expander bus device description, updates crs_range_set > and let the caller to enumerate buses and add descriptions to dsdt. > > Then after it we could do a generic csr generation function for the main pci host > if it's possible at all (main pci host csr seems heavily board depended) > > Instead of taking table and adding stuff directly in to it > it should be cleaner to take as argument empty csr (crs = aml_resource_template();) > add stuff to it and let the caller to add/extend csr as/where necessary. > > > +{ > > + CrsRangeEntry *entry; > > + Aml *scope, *dev, *crs; > > + CrsRangeSet crs_range_set; > > + Range *pci_hole = NULL; > > + Range *pci_hole64 = NULL; > > + PCIBus *bus = NULL; > > + int root_bus_limit = 0xFF; > > + int i; > > + > > + bus = pci_host->pci_bus; > > + assert(bus); > > + pci_hole = pci_host->pci_hole; > > + pci_hole64 = pci_host->pci_hole64; > > + > > + crs_range_set_init(&crs_range_set); > > + QLIST_FOREACH(bus, &bus->child, sibling) { > > + uint8_t bus_num = pci_bus_num(bus); > > + uint8_t numa_node = pci_bus_numa_node(bus); > > + > > + /* look only for expander root buses */ > > + if (!pci_bus_is_root(bus)) { > > + continue; > > + } > > + > > + if (bus_num < root_bus_limit) { > > + root_bus_limit = bus_num - 1; > > + } > > + > > + scope = aml_scope("\\_SB"); > > + dev = aml_device("PC%.02X", bus_num); > > + aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); > > + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); > > + aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); > > + if (pci_bus_is_express(bus)) { > > + aml_append(dev, aml_name_decl("SUPP", aml_int(0))); > > + aml_append(dev, aml_name_decl("CTRL", aml_int(0))); > > + aml_append(dev, build_osc_method(0x1F)); > > + } > > + if (numa_node != NUMA_NODE_UNASSIGNED) { > > + aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); > > + } > > + > > + aml_append(dev, build_prt(false)); > > + crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); > > + aml_append(dev, aml_name_decl("_CRS", crs)); > > + aml_append(scope, dev); > > + aml_append(table, scope); > > + } > > + scope = aml_scope("\\_SB.PCI0"); > > + /* build PCI0._CRS */ > > + crs = aml_resource_template(); > > + /* set the pcie bus num */ > > + aml_append(crs, > > + aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, > > + 0x0000, 0x0, root_bus_limit, > > + 0x0000, root_bus_limit + 1)); > > vvvv > > + aml_append(crs, aml_io(AML_DECODE16, PCI_HOST_BRIDGE_CONFIG_ADDR, > > + PCI_HOST_BRIDGE_CONFIG_ADDR, 0x01, 0x08)); > > + /* set the io region 0 in pci host bridge */ > > + aml_append(crs, > > + aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, > > + AML_POS_DECODE, AML_ENTIRE_RANGE, > > + 0x0000, PCI_HOST_BRIDGE_IO_0_MIN_ADDR, > > + PCI_HOST_BRIDGE_IO_0_MAX_ADDR, 0x0000, IO_0_LEN)); > > + > > + /* set the io region 1 in pci host bridge */ > > + crs_replace_with_free_ranges(crs_range_set.io_ranges, > > + PCI_HOST_BRIDGE_IO_1_MIN_ADDR, > > + PCI_HOST_BRIDGE_IO_1_MAX_ADDR); > above code doesn't look as just a movement, it's something totally new, > so it should be in it's own patch with a justification why it's ok > to replace concrete addresses with some kind of window. Ah I see your point now. Yes, I agree this should be in a separate patch. Cheers, Samuel.