Re: [PATCH] docs/memory-barriers.txt: Enforce heavy ordering for port I/O accesses

["Paul E. McKenney" <paulmck@linux.ibm.com>]

On Mon, Nov 26, 2018 at 08:33:49PM +0100, Andrea Parri wrote:
> On Mon, Nov 26, 2018 at 04:52:14PM +0000, Will Deacon wrote:
> > David Laight explains:
> > 
> >   | A long time ago there was a document from Intel that said that
> >   | inb/outb weren't necessarily synchronised wrt memory accesses.
> >   | (Might be P-pro era). However no processors actually behaved that
> >   | way and more recent docs say that inb/outb are fully ordered.
> 
> No intention to diminish David Laight's authority of course, but I would
> have really appreciated a reference to these "recent docs" (section, pg.
> or the like, especially if a reference manual...) here...

I would be inclined to cut Will a break given the research for his
recent talk on this topic, but it would be good to get an ack from
someone from Intel.  And memory-model patches require an ack or better
in any case.  ;-)

							Thanx, Paul

> > This also reflects the situation on other architectures, the the port
> > accessor macros tend to be implemented in terms of readX/writeX.
> > 
> > Update Documentation/memory-barriers.txt to reflect reality.
> 
> ..., IOW, what do you mean by "reality"?
> 
> > 
> > Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: David Laight <David.Laight@ACULAB.COM>
> > Cc: Alan Stern <stern@rowland.harvard.edu>
> > Cc: Peter Zijlstra <peterz@infradead.org>
> > Cc: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
> > Signed-off-by: Will Deacon <will.deacon@arm.com>
> 
> Please Cc me on future patches to memory-barriers.txt (can not speak for
> my co-maintainers, but I'm inclined to say that get_maintainers.pl knows
> better...).
> 
>   Andrea
> 
> 
> > ---
> > 
> > Just remembered I had this patch kicking around in my tree...
> > 
> >  Documentation/memory-barriers.txt | 6 ++----
> >  1 file changed, 2 insertions(+), 4 deletions(-)
> > 
> > diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
> > index c1d913944ad8..0c34c5dac138 100644
> > --- a/Documentation/memory-barriers.txt
> > +++ b/Documentation/memory-barriers.txt
> > @@ -2619,10 +2619,8 @@ functions:
> >       intermediary bridges (such as the PCI host bridge) may not fully honour
> >       that.
> >  
> > -     They are guaranteed to be fully ordered with respect to each other.
> > -
> > -     They are not guaranteed to be fully ordered with respect to other types of
> > -     memory and I/O operation.
> > +     They are guaranteed to be fully ordered with respect to each other and
> > +     also with respect to other types of memory and I/O operation.
> >  
> >   (*) readX(), writeX():
> >  
> > -- 
> > 2.1.4
> > 
>