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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id d67-v6si4593571ybb.324.2018.11.28.02.42.05 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 28 Nov 2018 02:42:06 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from localhost ([::1]:46984 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gRxID-0003Em-4B for alex.bennee@linaro.org; Wed, 28 Nov 2018 05:42:05 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57154) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gRxHC-0002zW-Oi for qemu-devel@nongnu.org; Wed, 28 Nov 2018 05:41:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gRxH8-00048O-04 for qemu-devel@nongnu.org; Wed, 28 Nov 2018 05:41:02 -0500 Received: from mga01.intel.com ([192.55.52.88]:59983) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gRxH7-00047c-NL; Wed, 28 Nov 2018 05:40:57 -0500 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Nov 2018 02:40:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,290,1539673200"; d="scan'208";a="287302242" Received: from bdoyle2-mobl.ger.corp.intel.com (HELO caravaggio) ([10.251.86.101]) by fmsmga005.fm.intel.com with ESMTP; 28 Nov 2018 02:40:54 -0800 Date: Wed, 28 Nov 2018 11:40:24 +0100 From: Samuel Ortiz To: Peter Maydell Message-ID: <20181128104024.GD4393@caravaggio> References: <20181113165247.4806-1-sameo@linux.intel.com> <20181113165247.4806-5-sameo@linux.intel.com> <20181127153551.GC4393@caravaggio> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.88 Subject: Re: [Qemu-devel] [PATCH 04/13] target: arm: Move all interrupt and exception handlers into their own file X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm , Richard Henderson , QEMU Developers Errors-To: qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-devel" X-TUID: cA2CjhUd2KPn On Tue, Nov 27, 2018 at 03:46:30PM +0000, Peter Maydell wrote: > On Tue, 27 Nov 2018 at 15:36, Samuel Ortiz wrote: > > > > On Tue, Nov 20, 2018 at 01:45:03PM +0000, Peter Maydell wrote: > > > What is your plan for dealing with the way that the KVM code > > > for injecting a breakpoint exception into the guest works > > > by calling the do_interrupt code ? > > > (see target/arm/kvm64.c:kvm_arm_handle_debug(), > > > which calls cc->do_interrupt(cs).) This patch moves those > > > functions to a file which won't be compiled and a later one > > > in the series seems to stop cc->do_interrupt being set at all > > > if CONFIG_TCG is not defined. That will result in QEMU crashing > > > when it tries to inject an exception, won't it? > > Yes, indeed. > > So it seems we need to inject an exception back into the guest when > > doing hardware assisted debugging and when we have not set any > > breakpoint from QEMU. So it's essentially handling the debugging from > > the guest case. > > Would returning an error when that happens be an acceptable solution? So > > when building qemu for arm64 with TCG disabled, one would basically no > > longer be able to debug from the guest. > > I don't think that's a good idea. --disable-tcg shouldn't imply > "and you lose some features of KVM". I see your point but as you're certainly aware, at the moment building with --disable-tcg implies you don't get an ARM QEMU binary at all. I felt this was an improvement over the current situation ;) > This code is used in both TCG > and KVM, so needs to still be in the binary for KVM. Given that this piece of code effectively builds a dependency to TCG from the KVM code, I see a few solutions but I need your input here. We could: - Decide we don't want to support --disable-tcg for ARM. We'd then carry this patch serie from the NEMU code repo. Worst case scenario, at least for us. - Manage to implement exception injection from userspace without TCG. Would it even be possible? - Offload exception injections back to the kernel in those cases. I feel this would be the cleanest solution but may need kernel changes. Any other suggestions? Cheers, Samuel.