From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jordan Crouse Subject: [PATCH 0/1] drm/msm/a6xx: Add interconnect support Date: Wed, 28 Nov 2018 11:29:28 -0700 Message-ID: <20181128182929.19925-1-jcrouse@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: freedreno-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Freedreno" To: georgi.djakov-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org Cc: linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: linux-arm-msm@vger.kernel.org SSBoZWFyZCBhdCBMUEMgdGhhdCB0aGVyZSB3YXMgc29tZSBjb25mdXNpb24gdGhhdCB0aGUgT1BQ IGJpbmRpbmdzIFsxXQp3ZXJlIG5lZWRlZCB0byBsYW5kIGludGVyY29ubmVjdCBzdXBwb3J0LiBU aGV5IGFyZW4ndC4KClRoZXJlIGlzIGEgdHdvIHN0ZXAgcHJvY2VzcyBmb3IgdGhlIFNETTg0NSBH UFUuIEZpcnN0IHdlIG5lZWQgYSB2b3RlIChhbnkgdm90ZSkKYmVjYXVzZSB0aGUgZGVmYXVsdCBi dXMgc2V0dGluZ3MgYXJlIHdheSB0b28gYmFkIGZvciBhbnkgcmVhc29uYWJsZQpwZXJmb3JtYW5j ZS4KClRoZSBuZXh0IHN0ZXAgYWZ0ZXIgdGhhdCB3b3VsZCBiZSB0byBzY2FsZSB0aGUgYnVzIHJl cXVlc3QgYmFzZWQgb24gdGhlCmZyZXF1ZW5jeSBpbiBvcmRlciB0byBzYXZlIHBvd2VyLiBGb3Ig dGhhdCB3ZSAqZG8qIG5lZWQgYSBzb2x1dGlvbiBidXQgdGhhdApjYW4gYmUgY2FsbWx5IGRpc2N1 c3NlZCBzZXBhcmF0ZWx5LgoKVGhpcyBwYXRjaCBhY2NvbW1vZGF0ZXMgdGhlIGZpcnN0IHN0ZXAu IEl0IGNyYW5rcyB0aGUgYnVzIHRvIG1heCBmb3IgR1BVCmFjdGl2aXR5IGFuZCB0dXJucyBpdCBv ZmYgd2hlbiB0aGUgR1BVIGdvZXMgdG8gc2xlZXAuIEhvcGVmdWxseSB0aGlzIGNhbgphbGxldmlh dGUgdGhlIGNvbmZ1c2lvbiBhbmQgaGVscCBpbnRlcmNvbm5lY3QgbGFuZCB0aGF0IG11Y2ggcXVp Y2tlci4KQWZ0ZXIgdGhhdCwgd2UgY2FuIGNhbG1seSByZS1pbnRyb2R1Y2UgdGhlIE9QUCBkaXNj dXNzaW9uLgoKVGhpcyBwYXRjaCBkZXBlbmRzIG9uIGludGVyY29ubmVjdCBzdXBwb3J0IFsyXS4K ClsxXSBodHRwczovL3BhdGNod29yay5rZXJuZWwub3JnL3BhdGNoLzEwNTc3MzAzLwpbMl0gaHR0 cHM6Ly9wYXRjaHdvcmsua2VybmVsLm9yZy9wYXRjaC8xMDcwMTI4Ny8KCkpvcmRhbiBDcm91c2Ug KDEpOgogIGRybS9tc20vYTZ4eDogQWRkIHN1cHBvcnQgZm9yIGFuIGludGVyY29ubmVjdCBwYXRo CgogZHJpdmVycy9ncHUvZHJtL21zbS9hZHJlbm8vYTZ4eF9nbXUuYyAgIHwgMjAgKysrKysrKysr KysrKysrKysrKysKIGRyaXZlcnMvZ3B1L2RybS9tc20vYWRyZW5vL2FkcmVub19ncHUuYyB8ICA5 ICsrKysrKysrKwogZHJpdmVycy9ncHUvZHJtL21zbS9tc21fZ3B1LmggICAgICAgICAgIHwgIDMg KysrCiAzIGZpbGVzIGNoYW5nZWQsIDMyIGluc2VydGlvbnMoKykKCi0tIAoyLjE4LjAKCl9fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCkZyZWVkcmVubyBtYWls aW5nIGxpc3QKRnJlZWRyZW5vQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZy ZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ZyZWVkcmVubwo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: jcrouse@codeaurora.org (Jordan Crouse) Date: Wed, 28 Nov 2018 11:29:28 -0700 Subject: [PATCH 0/1] drm/msm/a6xx: Add interconnect support Message-ID: <20181128182929.19925-1-jcrouse@codeaurora.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org I heard at LPC that there was some confusion that the OPP bindings [1] were needed to land interconnect support. They aren't. There is a two step process for the SDM845 GPU. First we need a vote (any vote) because the default bus settings are way too bad for any reasonable performance. The next step after that would be to scale the bus request based on the frequency in order to save power. For that we *do* need a solution but that can be calmly discussed separately. This patch accommodates the first step. It cranks the bus to max for GPU activity and turns it off when the GPU goes to sleep. Hopefully this can alleviate the confusion and help interconnect land that much quicker. After that, we can calmly re-introduce the OPP discussion. This patch depends on interconnect support [2]. [1] https://patchwork.kernel.org/patch/10577303/ [2] https://patchwork.kernel.org/patch/10701287/ Jordan Crouse (1): drm/msm/a6xx: Add support for an interconnect path drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 20 ++++++++++++++++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 +++++++++ drivers/gpu/drm/msm/msm_gpu.h | 3 +++ 3 files changed, 32 insertions(+) -- 2.18.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B91F9C43441 for ; Wed, 28 Nov 2018 18:29:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 78503206B6 for ; Wed, 28 Nov 2018 18:29:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="IF9etCmL"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="Jj/YAShB" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 78503206B6 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727197AbeK2FcJ (ORCPT ); Thu, 29 Nov 2018 00:32:09 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:52928 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725761AbeK2FcI (ORCPT ); Thu, 29 Nov 2018 00:32:08 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 21DB4601C4; Wed, 28 Nov 2018 18:29:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1543429775; bh=ei81HWo7Dpp6+q3denXZpXf2opNyFdYdoexeLRrE4IU=; h=From:To:Cc:Subject:Date:From; b=IF9etCmLvOqeJsIBHTg7xxItRauqVdW77d5R4wJWnsi6JeHbsn5qZ3xwyTIxsqZP8 EUkAbNJEy+oItg+tPNIHrMlDocKmgRqaz2BZ1YpWmyFX+0d7ZvVL/TNpDufI8vyLAc ckcwteSd4wt5VAoAa3WXyZKo5iOEGZkXxkPd2+L8= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 1D8CD601C4; Wed, 28 Nov 2018 18:29:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1543429774; bh=ei81HWo7Dpp6+q3denXZpXf2opNyFdYdoexeLRrE4IU=; h=From:To:Cc:Subject:Date:From; b=Jj/YAShBDC7Xx+HA6B/ortStT7Cu0Q/A+kWOwJqJFmOJBInW7AoA/6+QBxYLsnPeX NGDpzKexgyzvvhNlK8cdpTlBcgDs/KKAKPaoL33nLuHACpOZqr+6hZ5TZre0rl/BZj a8NFCbL8Z4ueVmWbKmimcGt4N1N/+IP01SVj50kU= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 1D8CD601C4 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: georgi.djakov@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 0/1] drm/msm/a6xx: Add interconnect support Date: Wed, 28 Nov 2018 11:29:28 -0700 Message-Id: <20181128182929.19925-1-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org I heard at LPC that there was some confusion that the OPP bindings [1] were needed to land interconnect support. They aren't. There is a two step process for the SDM845 GPU. First we need a vote (any vote) because the default bus settings are way too bad for any reasonable performance. The next step after that would be to scale the bus request based on the frequency in order to save power. For that we *do* need a solution but that can be calmly discussed separately. This patch accommodates the first step. It cranks the bus to max for GPU activity and turns it off when the GPU goes to sleep. Hopefully this can alleviate the confusion and help interconnect land that much quicker. After that, we can calmly re-introduce the OPP discussion. This patch depends on interconnect support [2]. [1] https://patchwork.kernel.org/patch/10577303/ [2] https://patchwork.kernel.org/patch/10701287/ Jordan Crouse (1): drm/msm/a6xx: Add support for an interconnect path drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 20 ++++++++++++++++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 +++++++++ drivers/gpu/drm/msm/msm_gpu.h | 3 +++ 3 files changed, 32 insertions(+) -- 2.18.0