From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/dp: Set the MOT bit for Write_Status_Update_Request transactions Date: Tue, 11 Dec 2018 15:22:31 +0200 Message-ID: <20181211132231.GP9144@intel.com> References: <20181210210749.20649-1-dhinakaran.pandiyan@intel.com> <20181210212906.GN9144@intel.com> <991045e8250f328eef71c4d3036bdfd6b98cc3a8.camel@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <991045e8250f328eef71c4d3036bdfd6b98cc3a8.camel@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Dhinakaran Pandiyan Cc: Jani Nikula , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org T24gTW9uLCBEZWMgMTAsIDIwMTggYXQgMDI6MTU6MTFQTSAtMDgwMCwgRGhpbmFrYXJhbiBQYW5k aXlhbiB3cm90ZToKPiBPbiBNb24sIDIwMTgtMTItMTAgYXQgMjM6MjkgKzAyMDAsIFZpbGxlIFN5 cmrDpGzDpCB3cm90ZToKPiA+IE9uIE1vbiwgRGVjIDEwLCAyMDE4IGF0IDAxOjA3OjQ5UE0gLTA4 MDAsIERoaW5ha2FyYW4gUGFuZGl5YW4gd3JvdGU6Cj4gPiA+IFRoZSBXcml0ZV9TdGF0dXNfVXBk YXRlX1JlcXVlc3QgSTJDIHRyYW5zYWN0aW9uIHJlcXVpcmVzIHRoZSBNT1QKPiA+ID4gYml0IHRv Cj4gPiA+IGJlIHNldCwgQ2hhbmdlIHRoZSBsb2dpY2FsIEFORCB0byBPUiB0byBmaXggd2hhdCBs b29rcyBsaWtlIGEgdHlwby4KPiA+IAo+ID4gSXQncyBub3QgYSB0eXBlLiBXZSdyZSBqdXN0IHBy ZXNlcnZpbmcgTU9ULiBXaGF0IG1ha2VzIHlvdSB0aGluayBpdAo+ID4gc2hvdWxkIGFsd2F5cyBi ZSBzZXQ/Cj4gPiAKPiBUaGUgdGFibGUgZGVmaW5pbmcgcmVxdWVzdCBjb21tYW5kcyAoMi0xNDgp IGhhcyB0aGUgTU9UIGJpdCBzZXQgZm9yCj4gV3JpdGVfU3RhdHVzX1VwZGF0ZV9SZXF1ZXN0LCBk b2Vzbid0IG1ha2UgaXQgbG9vayBsaWtlIGFuIG9wdGlvbiB3aGVuCj4gcXVlcnlpbmcgdGhlIHN0 YXR1cy4gQ2hlY2tpbmcgdGhlIGNhbGxlcnMgYWdhaW4sIEkgc2VlIHRoYXQgd2UgY291bGQKPiBn ZXQgYSBkZWZlciB3aGVuIGVuZGluZyBhbiBpMmMgdHJhbnNhY3Rpb24gYW5kIHRoYXQgd2lsbCBy ZXF1aXJlIGEKPiBXcml0ZV9TdGF0dXNfVXBkYXRlX1JlcXVlc3Qgd2l0aCBNT1QgdW5zZXQuIFNv cnJ5IGZvciB0aGUgbm9pc2UuCgpPciBhIHNob3J0IHJlcGx5LiBBZG1pdHRlZGx5IHRoZSBzcGVj IGlzIGEgYml0IHZhZ3VlIG9uIHRoaXMgdG9waWMsCmJ1dCBhZnRlciB0cmF3bGluZyBpdCB0aG9y b3VnbHkgYWdhaW4gSSBzcG90dGVkIHRoYXQgdGFibGUgMi0xNTEgIzkKZG9lcyBoYXZlIGFuIGV4 YW1wbGUgb2Ygd3JpdGVfc3RhdHVzX3VwZGF0ZSB3aXRoIG1vdD09MC4gU28gSSBndWVzcwpteSBv cmlnaW5hbCBpbnRlcnByZXRhdGlvbiB3YXMgaW4gZmFjdCBjb3JyZWN0LiBQaGV3IDopCgo+IAo+ IAo+IAo+IAo+ID4gPiAKPiA+ID4gQ2M6IGRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcK PiA+ID4gQ2M6IEphbmkgTmlrdWxhIDxqYW5pLm5pa3VsYUBpbnRlbC5jb20+Cj4gPiA+IENjOiBW aWxsZSBTeXJqw6Rsw6QgPHZpbGxlLnN5cmphbGFAbGludXguaW50ZWwuY29tPgo+ID4gPiBGaXhl czogNjhlYzJhMmEyNDgxICgiZHJtL2RwOiBVc2UgSTJDX1dSSVRFX1NUQVRVU19VUERBVEUgdG8g ZHJhaW4KPiA+ID4gcGFydGlhbCBJMkNfV1JJVEUgcmVxdWVzdHMiKQo+ID4gPiBTaWduZWQtb2Zm LWJ5OiBEaGluYWthcmFuIFBhbmRpeWFuIDxkaGluYWthcmFuLnBhbmRpeWFuQGludGVsLmNvbT4K PiA+ID4gLS0tCj4gPiA+ICBkcml2ZXJzL2dwdS9kcm0vZHJtX2RwX2hlbHBlci5jIHwgMiArLQo+ ID4gPiAgMSBmaWxlIGNoYW5nZWQsIDEgaW5zZXJ0aW9uKCspLCAxIGRlbGV0aW9uKC0pCj4gPiA+ IAo+ID4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2RybV9kcF9oZWxwZXIuYwo+ID4g PiBiL2RyaXZlcnMvZ3B1L2RybS9kcm1fZHBfaGVscGVyLmMKPiA+ID4gaW5kZXggMmQ2YzQ5MWEw NTQyLi5kOTg4MDViNTE3ZjAgMTAwNjQ0Cj4gPiA+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9kcm1f ZHBfaGVscGVyLmMKPiA+ID4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2RybV9kcF9oZWxwZXIuYwo+ ID4gPiBAQCAtNjc3LDcgKzY3Nyw3IEBAIHN0YXRpYyB2b2lkCj4gPiA+IGRybV9kcF9pMmNfbXNn X3dyaXRlX3N0YXR1c191cGRhdGUoc3RydWN0IGRybV9kcF9hdXhfbXNnICptc2cpCj4gPiA+ICAJ ICogcmVzdCBvZiB0aGUgbWVzc2FnZQo+ID4gPiAgCSAqLwo+ID4gPiAgCWlmICgobXNnLT5yZXF1 ZXN0ICYgfkRQX0FVWF9JMkNfTU9UKSA9PSBEUF9BVVhfSTJDX1dSSVRFKSB7Cj4gPiA+IC0JCW1z Zy0+cmVxdWVzdCAmPSBEUF9BVVhfSTJDX01PVDsKPiA+ID4gKwkJbXNnLT5yZXF1ZXN0IHw9IERQ X0FVWF9JMkNfTU9UOwo+ID4gPiAgCQltc2ctPnJlcXVlc3QgfD0gRFBfQVVYX0kyQ19XUklURV9T VEFUVVNfVVBEQVRFOwo+ID4gPiAgCX0KPiA+ID4gIH0KPiA+ID4gLS0gCj4gPiA+IDIuMTcuMQo+ ID4gCj4gPiAKCi0tIApWaWxsZSBTeXJqw6Rsw6QKSW50ZWwKX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2 ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21h aWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg==