Re: [PATCH] drm/i915: Don't forget to reset blocks when testing lower wm levels

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Wed, Dec 12, 2018 at 11:17:20AM -0800, Matt Roper wrote:
> During DDB allocation, we try to distribute enough blocks for each plane
> to hit the highest watermark level; if that fails, we retry each lower
> level (which should require fewer blocks) until we find one that's
> possible (or until the whole commit is rejected as impossible).  We need
> to reset our running block count when trying each lower level, otherwise
> all lower levels will fail as well.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Fixes: d8e8749802 ("drm/i915: Switch to level-based DDB allocation algorithm (v5)")
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Whoops.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
> After waiting for CI results to come out, I accidentally pushed v5 of
> the new DDB algorithm rather than the expected v6.  This fixup patch is
> the only difference between those two versions.
> 
>  drivers/gpu/drm/i915/intel_pm.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6d074f2e69d3..a6c7c11d2c0e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4365,6 +4365,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
>  	 * requirement of active planes.
>  	 */
>  	for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
> +		blocks = 0;
>  		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
>  			if (plane_id == PLANE_CURSOR)
>  				continue;
> -- 
> 2.14.4

-- 
Ville Syrjälä
Intel
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