From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.9 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC5FEC65BAE for ; Thu, 13 Dec 2018 14:36:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 885DB20989 for ; Thu, 13 Dec 2018 14:36:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 885DB20989 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-pci-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727618AbeLMOg2 (ORCPT ); Thu, 13 Dec 2018 09:36:28 -0500 Received: from mail.bootlin.com ([62.4.15.54]:53932 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728097AbeLMOg2 (ORCPT ); Thu, 13 Dec 2018 09:36:28 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id CFC552079D; Thu, 13 Dec 2018 15:36:25 +0100 (CET) Received: from windsurf (aaubervilliers-681-1-89-7.w90-88.abo.wanadoo.fr [90.88.30.7]) by mail.bootlin.com (Postfix) with ESMTPSA id E77C420DDA; Thu, 13 Dec 2018 15:36:19 +0100 (CET) Date: Thu, 13 Dec 2018 15:36:19 +0100 From: Thomas Petazzoni To: Miquel Raynal Cc: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Bjorn Helgaas , , Rob Herring , Mark Rutland , Lorenzo Pieralisi , linux-pci@vger.kernel.org, , , Antoine Tenart , Maxime Chevallier , Nadav Haklai Subject: Re: [PATCH v2 10/12] ARM64: dts: marvell: armada-3720-espressobin: declare PCIe reset GPIO Message-ID: <20181213153619.499aab66@windsurf> In-Reply-To: <20181213153306.4fc3b511@xps13> References: <20181212102142.16053-1-miquel.raynal@bootlin.com> <20181212102142.16053-11-miquel.raynal@bootlin.com> <20181213153306.4fc3b511@xps13> Organization: Bootlin X-Mailer: Claws Mail 3.16.0 (GTK+ 2.24.32; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Hello, On Thu, 13 Dec 2018 15:33:06 +0100, Miquel Raynal wrote: > I will re-send a series without this patch. I think it does not hurt to > keep the previous patch adding the pinmux setting in the > Armada-37xx.dtsi file even without using it, so I will drop only this > patch. I tend to disagree here (but perhaps you'll have other arguments to convince me otherwise): the GPIO used for PCIe reset is a completely board-specific thing. You can chose whatever GPIO you want, and each board can be different. Therefore, there is no reason to have such a pinmux configuration at the SoC level (.dtsi), it should be within the particular board that uses that pinmux configuration. This is a rule that we have applied to mvebu platforms in general, and which I believe is fairly common in many DTs. Best regards, Thomas -- Thomas Petazzoni, CTO, Bootlin Embedded Linux and Kernel engineering https://bootlin.com From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D3A1C67839 for ; Thu, 13 Dec 2018 14:36:44 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3DB8220849 for ; Thu, 13 Dec 2018 14:36:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="rULZeFYJ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3DB8220849 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1wCfe4L11rBrkheUIhKNGAuKLOh9ULqJcNa4tsMAldE=; b=rULZeFYJUcx3Cj whZNH246gt0xR5gGSi9o5i6CQ1DA+qWCwmT6ltR4reW8arnB5pruuoof6je6tGCliiONH4o9H7+G9 cXSCbOhV8kGDLnaTyZyl/jJihxd6ciTq03dIs6ac5nVa86qO+A0z2mGzqos25ZYLA5M5Zb4YmcV9b N1c+EvEIVwcQnjs7z3pqroaAZz4YzR97JRa7Es53xpEWJ3s2nw0PzmXCaEcuhfzq47M28P8jNzZ4C PGWxwcRRjSKwLj2/Nvg7tgadl4CgjPO0Sa331R/0bbO9AeD37B2k83+KwMkNrzYCtBnPQTM2WJsnw o4zvyVTD+I+G+5c+i8Wg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gXS6V-0000JF-3S; Thu, 13 Dec 2018 14:36:43 +0000 Received: from mail.bootlin.com ([62.4.15.54]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gXS6Q-0000GV-Bv for linux-arm-kernel@lists.infradead.org; Thu, 13 Dec 2018 14:36:40 +0000 Received: by mail.bootlin.com (Postfix, from userid 110) id CFC552079D; Thu, 13 Dec 2018 15:36:25 +0100 (CET) Received: from windsurf (aaubervilliers-681-1-89-7.w90-88.abo.wanadoo.fr [90.88.30.7]) by mail.bootlin.com (Postfix) with ESMTPSA id E77C420DDA; Thu, 13 Dec 2018 15:36:19 +0100 (CET) Date: Thu, 13 Dec 2018 15:36:19 +0100 From: Thomas Petazzoni To: Miquel Raynal Subject: Re: [PATCH v2 10/12] ARM64: dts: marvell: armada-3720-espressobin: declare PCIe reset GPIO Message-ID: <20181213153619.499aab66@windsurf> In-Reply-To: <20181213153306.4fc3b511@xps13> References: <20181212102142.16053-1-miquel.raynal@bootlin.com> <20181212102142.16053-11-miquel.raynal@bootlin.com> <20181213153306.4fc3b511@xps13> Organization: Bootlin X-Mailer: Claws Mail 3.16.0 (GTK+ 2.24.32; x86_64-redhat-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181213_063638_536886_2562F8A3 X-CRM114-Status: GOOD ( 12.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Andrew Lunn , Lorenzo Pieralisi , Jason Cooper , devicetree@vger.kernel.org, Antoine Tenart , linux-pci@vger.kernel.org, Gregory Clement , linux-kernel@vger.kernel.org, Maxime Chevallier , Nadav Haklai , Rob Herring , Bjorn Helgaas , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello, On Thu, 13 Dec 2018 15:33:06 +0100, Miquel Raynal wrote: > I will re-send a series without this patch. I think it does not hurt to > keep the previous patch adding the pinmux setting in the > Armada-37xx.dtsi file even without using it, so I will drop only this > patch. I tend to disagree here (but perhaps you'll have other arguments to convince me otherwise): the GPIO used for PCIe reset is a completely board-specific thing. You can chose whatever GPIO you want, and each board can be different. Therefore, there is no reason to have such a pinmux configuration at the SoC level (.dtsi), it should be within the particular board that uses that pinmux configuration. This is a rule that we have applied to mvebu platforms in general, and which I believe is fairly common in many DTs. Best regards, Thomas -- Thomas Petazzoni, CTO, Bootlin Embedded Linux and Kernel engineering https://bootlin.com _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Petazzoni Subject: Re: [PATCH v2 10/12] ARM64: dts: marvell: armada-3720-espressobin: declare PCIe reset GPIO Date: Thu, 13 Dec 2018 15:36:19 +0100 Message-ID: <20181213153619.499aab66@windsurf> References: <20181212102142.16053-1-miquel.raynal@bootlin.com> <20181212102142.16053-11-miquel.raynal@bootlin.com> <20181213153306.4fc3b511@xps13> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20181213153306.4fc3b511@xps13> Sender: linux-kernel-owner@vger.kernel.org To: Miquel Raynal Cc: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Bjorn Helgaas , devicetree@vger.kernel.org, Rob Herring , Mark Rutland , Lorenzo Pieralisi , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Antoine Tenart , Maxime Chevallier , Nadav Haklai List-Id: devicetree@vger.kernel.org Hello, On Thu, 13 Dec 2018 15:33:06 +0100, Miquel Raynal wrote: > I will re-send a series without this patch. I think it does not hurt to > keep the previous patch adding the pinmux setting in the > Armada-37xx.dtsi file even without using it, so I will drop only this > patch. I tend to disagree here (but perhaps you'll have other arguments to convince me otherwise): the GPIO used for PCIe reset is a completely board-specific thing. You can chose whatever GPIO you want, and each board can be different. Therefore, there is no reason to have such a pinmux configuration at the SoC level (.dtsi), it should be within the particular board that uses that pinmux configuration. This is a rule that we have applied to mvebu platforms in general, and which I believe is fairly common in many DTs. Best regards, Thomas -- Thomas Petazzoni, CTO, Bootlin Embedded Linux and Kernel engineering https://bootlin.com