From: Angelo Dureghello <angelo@sysam.it>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v4 12/12] m68k: move dspi bus control functions into cf_spi.c driver
Date: Sun, 16 Dec 2018 12:23:00 +0100 [thread overview]
Message-ID: <20181216112300.9367-12-angelo@sysam.it> (raw)
In-Reply-To: <20181216112300.9367-1-angelo@sysam.it>
This patches move dspi bus-related operations into more
proper location, to avoid the driver to declares them as externs.
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
Changes for v4:
- new patch
---
arch/m68k/cpu/mcf5227x/cpu_init.c | 65 +++-----------
arch/m68k/cpu/mcf5445x/cpu_init.c | 142 +++++++-----------------------
2 files changed, 41 insertions(+), 166 deletions(-)
diff --git a/arch/m68k/cpu/mcf5227x/cpu_init.c b/arch/m68k/cpu/mcf5227x/cpu_init.c
index 0d6a484a45..3bbc42f508 100644
--- a/arch/m68k/cpu/mcf5227x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5227x/cpu_init.c
@@ -16,6 +16,15 @@
#include <asm/rtc.h>
#include <linux/compiler.h>
+void cfspi_port_conf(void)
+{
+ gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+ out_8(&gpio->par_dspi,
+ GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+ GPIO_PAR_DSPI_SCK_SCK);
+}
+
/*
* Breath some life into the CPU...
*
@@ -93,6 +102,8 @@ void cpu_init_f(void)
#endif
icache_enable();
+
+ cfspi_port_conf();
}
/*
@@ -137,57 +148,3 @@ void uart_port_conf(int port)
break;
}
}
-
-#ifdef CONFIG_CF_DSPI
-void cfspi_port_conf(void)
-{
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- out_8(&gpio->par_dspi,
- GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
- GPIO_PAR_DSPI_SCK_SCK);
-}
-
-int cfspi_claim_bus(uint bus, uint cs)
-{
- dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
- return -1;
-
- /* Clear FIFO and resume transfer */
- clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 2:
- clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
- setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
- break;
- }
-
- return 0;
-}
-
-void cfspi_release_bus(uint bus, uint cs)
-{
- dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- /* Clear FIFO */
- clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 2:
- clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
- break;
- }
-}
-#endif
diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c
index 7632d9262c..8f4991c1cb 100644
--- a/arch/m68k/cpu/mcf5445x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5445x/cpu_init.c
@@ -66,6 +66,32 @@ void init_fbcs(void)
#endif
}
+#ifdef CONFIG_CF_DSPI
+void cfspi_port_conf(void)
+{
+ gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+#ifdef CONFIG_MCF5445x
+ out_8(&gpio->par_dspi,
+ GPIO_PAR_DSPI_SIN_SIN |
+ GPIO_PAR_DSPI_SOUT_SOUT |
+ GPIO_PAR_DSPI_SCK_SCK);
+#endif
+
+#ifdef CONFIG_MCF5441x
+ pm_t *pm = (pm_t *)MMAP_PM;
+
+ out_8(&gpio->par_dspi0,
+ GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
+ GPIO_PAR_DSPI0_SCK_DSPI0SCK);
+ out_8(&gpio->srcr_dspiow, 3);
+
+ /* DSPI0 */
+ out_8(&pm->pmcr0, 23);
+#endif
+}
+#endif
+
/*
* Breath some life into the CPU...
*
@@ -204,6 +230,10 @@ void cpu_init_f(void)
GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
+#ifdef CONFIG_CF_SPI
+ cfspi_port_conf();
+#endif
+
#ifdef CONFIG_SYS_FSL_I2C
out_be16(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
@@ -433,115 +463,3 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
}
#endif
-#ifdef CONFIG_CF_DSPI
-void cfspi_port_conf(void)
-{
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-#ifdef CONFIG_MCF5445x
- out_8(&gpio->par_dspi,
- GPIO_PAR_DSPI_SIN_SIN |
- GPIO_PAR_DSPI_SOUT_SOUT |
- GPIO_PAR_DSPI_SCK_SCK);
-#endif
-
-#ifdef CONFIG_MCF5441x
- pm_t *pm = (pm_t *) MMAP_PM;
-
- out_8(&gpio->par_dspi0,
- GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
- GPIO_PAR_DSPI0_SCK_DSPI0SCK);
- out_8(&gpio->srcr_dspiow, 3);
-
- /* DSPI0 */
- out_8(&pm->pmcr0, 23);
-#endif
-}
-
-int cfspi_claim_bus(uint bus, uint cs)
-{
- dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
- return -1;
-
- /* Clear FIFO and resume transfer */
- clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
-#ifdef CONFIG_MCF5445x
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 1:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
- break;
- case 2:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
- break;
- case 3:
- clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
- setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
- break;
- case 5:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
- break;
- }
-#endif
-
-#ifdef CONFIG_MCF5441x
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK);
- setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
- break;
- case 1:
- clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
- setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
- break;
- }
-#endif
-
- return 0;
-}
-
-void cfspi_release_bus(uint bus, uint cs)
-{
- dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- /* Clear FIFO */
- clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
-#ifdef CONFIG_MCF5445x
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 1:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
- break;
- case 2:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
- break;
- case 3:
- clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
- break;
- case 5:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
- break;
- }
-#endif
-
-#ifdef CONFIG_MCF5441x
- if (cs == 1)
- clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
-#endif
-}
-
-#endif
--
2.19.1
prev parent reply other threads:[~2018-12-16 11:23 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-16 11:22 [U-Boot] [PATCH v4 01/12] m68k: add basic set of devicetrees Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 02/12] m68k: architecture changes to support fdt Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 03/12] m68k: add initial dts files for all m68k boards Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 04/12] m68k: enabling long jumps on mcf54x5 SoCs Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 05/12] configs: enable use of DT for all m68k boards Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 06/12] drivers: spi: cf_spi: add Kconfig option Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 07/12] drivers: spi: cf_spi: convert to driver model Angelo Dureghello
2019-03-08 6:00 ` Jagan Teki
2019-03-10 16:17 ` Angelo Dureghello
2019-03-11 17:34 ` Jagan Teki
2018-12-16 11:22 ` [U-Boot] [PATCH v4 08/12] configs: add DM_SPI config option Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 09/12] drivers: serial: mcfuart: add DT support Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 10/12] configs: remove CONFIG_SYS_DSPI_XX references Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 11/12] m68k: add OF control support to m68k Angelo Dureghello
2018-12-16 11:23 ` Angelo Dureghello [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20181216112300.9367-12-angelo@sysam.it \
--to=angelo@sysam.it \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.