From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH v6 1/2] dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings Date: Mon, 17 Dec 2018 15:20:10 -0600 Message-ID: <20181217212010.GA22389@bogus> References: <20181212211848.26768-1-jcrouse@codeaurora.org> <20181212211848.26768-2-jcrouse@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <20181212211848.26768-2-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: freedreno-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Freedreno" To: Jordan Crouse Cc: nm-l0cyMroinI0@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, rnayak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, 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[70.114.214.127]) by smtp.gmail.com with ESMTPSA id k13sm11782125otj.19.2018.12.17.13.20.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 13:20:11 -0800 (PST) Date: Mon, 17 Dec 2018 15:20:10 -0600 From: Rob Herring To: Jordan Crouse Subject: Re: [PATCH v6 1/2] dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings Message-ID: <20181217212010.GA22389@bogus> References: <20181212211848.26768-1-jcrouse@codeaurora.org> <20181212211848.26768-2-jcrouse@codeaurora.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20181212211848.26768-2-jcrouse@codeaurora.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181217_132023_340570_1FD382B9 X-CRM114-Status: GOOD ( 23.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nm@ti.com, devicetree@vger.kernel.org, rnayak@codeaurora.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, dianders@chromium.org, dri-devel@lists.freedesktop.org, vireshk@kernel.org, freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Dec 12, 2018 at 02:18:47PM -0700, Jordan Crouse wrote: > Update the GPU bindings and document the new bindings for the GMU > device found with Adreno a6xx targets. > > Signed-off-by: Jordan Crouse > --- > .../devicetree/bindings/display/msm/gmu.txt | 56 +++++++++++++++++++ > .../devicetree/bindings/display/msm/gpu.txt | 41 +++++++++++++- > 2 files changed, 94 insertions(+), 3 deletions(-) > create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt > > diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt b/Documentation/devicetree/bindings/display/msm/gmu.txt > new file mode 100644 > index 000000000000..6152cb551d29 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/gmu.txt > @@ -0,0 +1,56 @@ > +Qualcomm adreno/snapdragon GMU (Graphics management unit) > + > +The GMU is a programmable power controller for the GPU. the CPU controls the > +GMU which in turn handles power controls for the GPU. > + > +Required properties: > +- compatible: > + * "qcom,adreno-gmu" I probably asked before, but this needs a specific compatible unless you have reliable version/capability registers. If you do, please state that here. > +- reg: Physical base address and length of the GMU registers. > +- reg-names: Matching names for the register regions > + * "gmu" > + * "gmu_pdc" > + * "gmu_pdc_seg" > +- interrupts: The interrupt signals from the GMU. > +- interrupt-names: Matching names for the interrupts > + * "hfi" > + * "gmu" > +- clocks: phandles to the device clocks > +- clock-names: Matching names for the clocks > + * "gmu" > + * "cxo" > + * "axi" > + * "mnoc" > +- power-domains: should be <&clock_gpucc GPU_CX_GDSC> > +- iommus: phandle to the adreno iommu > +- operating-points-v2: phandle to the OPP operating points > + > +Example: > + > +/ { > + ... > + > + gmu: gmu@506a000 { > + compatible="qcom,adreno-gmu"; > + > + reg = <0x506a000 0x30000>, > + <0xb280000 0x10000>, > + <0xb480000 0x10000>; > + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; > + > + interrupts = , > + ; > + interrupt-names = "hfi", "gmu"; > + > + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, > + <&gpucc GPU_CC_CXO_CLK>, > + <&gcc GCC_DDRSS_GPU_AXI_CLK>, > + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; > + clock-names = "gmu", "cxo", "axi", "memnoc"; > + > + power-domains = <&gpucc GPU_CX_GDSC>; > + iommus = <&adreno_smmu 5>; > + > + operating-points-v2 = <&gmu_opp_table>; > + }; > +}; > diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt > index 43fac0fe09bb..8d9415180c22 100644 > --- a/Documentation/devicetree/bindings/display/msm/gpu.txt > +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt > @@ -8,14 +8,21 @@ Required properties: > with the chip-id. > - reg: Physical base address and length of the controller's registers. > - interrupts: The interrupt signal from the gpu. > -- clocks: device clocks > +- interrupt-names: List of names for the interrupt signals. The following can be > + provided: > + * "kgsl_3d0_irq" I'm pretty sure 'kgsl' is not a hardware thing. You don't need *-names when there is only one of something. > +- clocks: device clocks (if applicable) What does this mean? They are now optional? If so, move to an "Optional" section. Likewise for the others. Really, you should add a new compatible so we can validate when clocks not being present is valid vs. an error in the DT. > See ../clocks/clock-bindings.txt for details. > -- clock-names: the following clocks are required: > +- clock-names: the following clocks can be provided: > * "core" > * "iface" > * "mem_iface" > +- iommus: optional phandle to an adreno iommu instance > +- operating-points-v2: optional phandle to the OPP operating points > +- qcom,gmu: For a6xx and newer targets a phandle to the GMU device that will > + control the power for the GPU _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel