From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jordan Crouse Subject: [PATCH v7 5/6] dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings Date: Tue, 18 Dec 2018 11:32:40 -0700 Message-ID: <20181218183241.12830-6-jcrouse@codeaurora.org> References: <20181218183241.12830-1-jcrouse@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20181218183241.12830-1-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: freedreno-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Freedreno" To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: nm-l0cyMroinI0@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, rnayak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, vireshk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, georgi.djakov-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: linux-arm-msm@vger.kernel.org VXBkYXRlIHRoZSBHUFUgYmluZGluZ3MgYW5kIGRvY3VtZW50IHRoZSBuZXcgYmluZGluZ3MgZm9y IHRoZSBHTVUKZGV2aWNlIGZvdW5kIHdpdGggQWRyZW5vIGE2eHggdGFyZ2V0cy4KClNpZ25lZC1v ZmYtYnk6IEpvcmRhbiBDcm91c2UgPGpjcm91c2VAY29kZWF1cm9yYS5vcmc+Ci0tLQoKdjc6IFVw ZGF0ZWQgdGhlIEdNVSBjb21wYXRpYmxlIHN0cmluZyBhbmQgY2xhcmlmaWVkIGRldGFpbHMgYWJv dXQgd2hlbiBjbG9ja3MKY2FuIGJlIG9wdGlvbmFsIG9uIHRoZSBHUFUKCiAuLi4vZGV2aWNldHJl ZS9iaW5kaW5ncy9kaXNwbGF5L21zbS9nbXUudHh0ICAgfCA1OSArKysrKysrKysrKysrKysrKysr CiAuLi4vZGV2aWNldHJlZS9iaW5kaW5ncy9kaXNwbGF5L21zbS9ncHUudHh0ICAgfCA0MiArKysr KysrKysrKystCiAyIGZpbGVzIGNoYW5nZWQsIDk4IGluc2VydGlvbnMoKyksIDMgZGVsZXRpb25z KC0pCiBjcmVhdGUgbW9kZSAxMDA2NDQgRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdz L2Rpc3BsYXkvbXNtL2dtdS50eHQKCmRpZmYgLS1naXQgYS9Eb2N1bWVudGF0aW9uL2RldmljZXRy ZWUvYmluZGluZ3MvZGlzcGxheS9tc20vZ211LnR4dCBiL0RvY3VtZW50YXRpb24vZGV2aWNldHJl ZS9iaW5kaW5ncy9kaXNwbGF5L21zbS9nbXUudHh0Cm5ldyBmaWxlIG1vZGUgMTAwNjQ0CmluZGV4 IDAwMDAwMDAwMDAwMC4uNTllNjg2NTg5OGYyCi0tLSAvZGV2L251bGwKKysrIGIvRG9jdW1lbnRh dGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL2Rpc3BsYXkvbXNtL2dtdS50eHQKQEAgLTAsMCArMSw1 OSBAQAorUXVhbGNvbW0gYWRyZW5vL3NuYXBkcmFnb24gR01VIChHcmFwaGljcyBtYW5hZ2VtZW50 IHVuaXQpCisKK1RoZSBHTVUgaXMgYSBwcm9ncmFtbWFibGUgcG93ZXIgY29udHJvbGxlciBmb3Ig dGhlIEdQVS4gdGhlIENQVSBjb250cm9scyB0aGUKK0dNVSB3aGljaCBpbiB0dXJuIGhhbmRsZXMg cG93ZXIgY29udHJvbHMgZm9yIHRoZSBHUFUuCisKK1JlcXVpcmVkIHByb3BlcnRpZXM6CistIGNv bXBhdGlibGU6ICJxY29tLGFkcmVuby1nbXUtWFlaLlciLCAicWNvbSxhZHJlbm8tZ211IgorICAg IGZvciBleGFtcGxlOiAicWNvbSxhZHJlbm8tZ211LTYzMC4yIiwgInFjb20sYWRyZW5vLWdtdSIK KyAgTm90ZSB0aGF0IHlvdSBuZWVkIHRvIGxpc3QgdGhlIGxlc3Mgc3BlY2lmaWMgInFjb20sYWRy ZW5vLWdtdSIKKyAgZm9yIGdlbmVyaWMgbWF0Y2hlcyBhbmQgdGhlIG1vcmUgc3BlY2lmaWMgaWRl bnRpZmllciB0byBpZGVudGlmeQorICB0aGUgc3BlY2lmaWMgZGV2aWNlLgorLSByZWc6IFBoeXNp Y2FsIGJhc2UgYWRkcmVzcyBhbmQgbGVuZ3RoIG9mIHRoZSBHTVUgcmVnaXN0ZXJzLgorLSByZWct bmFtZXM6IE1hdGNoaW5nIG5hbWVzIGZvciB0aGUgcmVnaXN0ZXIgcmVnaW9ucworICAqICJnbXUi CisgICogImdtdV9wZGMiCisgICogImdtdV9wZGNfc2VnIgorLSBpbnRlcnJ1cHRzOiBUaGUgaW50 ZXJydXB0IHNpZ25hbHMgZnJvbSB0aGUgR01VLgorLSBpbnRlcnJ1cHQtbmFtZXM6IE1hdGNoaW5n IG5hbWVzIGZvciB0aGUgaW50ZXJydXB0cworICAqICJoZmkiCisgICogImdtdSIKKy0gY2xvY2tz OiBwaGFuZGxlcyB0byB0aGUgZGV2aWNlIGNsb2NrcworLSBjbG9jay1uYW1lczogTWF0Y2hpbmcg bmFtZXMgZm9yIHRoZSBjbG9ja3MKKyAgICogImdtdSIKKyAgICogImN4byIKKyAgICogImF4aSIK KyAgICogIm1ub2MiCistIHBvd2VyLWRvbWFpbnM6IHNob3VsZCBiZSA8JmNsb2NrX2dwdWNjIEdQ VV9DWF9HRFNDPgorLSBpb21tdXM6IHBoYW5kbGUgdG8gdGhlIGFkcmVubyBpb21tdQorLSBvcGVy YXRpbmctcG9pbnRzLXYyOiBwaGFuZGxlIHRvIHRoZSBPUFAgb3BlcmF0aW5nIHBvaW50cworCitF eGFtcGxlOgorCisvIHsKKwkuLi4KKworCWdtdTogZ211QDUwNmEwMDAgeworCQljb21wYXRpYmxl PSJxY29tLGFkcmVuby1nbXUtNjMwLjIiLCAicWNvbSxhZHJlbm8tZ211IjsKKworCQlyZWcgPSA8 MHg1MDZhMDAwIDB4MzAwMDA+LAorCQkJPDB4YjI4MDAwMCAweDEwMDAwPiwKKwkJCTwweGI0ODAw MDAgMHgxMDAwMD47CisJCXJlZy1uYW1lcyA9ICJnbXUiLCAiZ211X3BkYyIsICJnbXVfcGRjX3Nl cSI7CisKKwkJaW50ZXJydXB0cyA9IDxHSUNfU1BJIDMwNCBJUlFfVFlQRV9MRVZFTF9ISUdIPiwK KwkJICAgICA8R0lDX1NQSSAzMDUgSVJRX1RZUEVfTEVWRUxfSElHSD47CisJCWludGVycnVwdC1u YW1lcyA9ICJoZmkiLCAiZ211IjsKKworCQljbG9ja3MgPSA8JmdwdWNjIEdQVV9DQ19DWF9HTVVf Q0xLPiwKKwkJCTwmZ3B1Y2MgR1BVX0NDX0NYT19DTEs+LAorCQkJPCZnY2MgR0NDX0REUlNTX0dQ VV9BWElfQ0xLPiwKKwkJCTwmZ2NjIEdDQ19HUFVfTUVNTk9DX0dGWF9DTEs+OworCQljbG9jay1u YW1lcyA9ICJnbXUiLCAiY3hvIiwgImF4aSIsICJtZW1ub2MiOworCisJCXBvd2VyLWRvbWFpbnMg PSA8JmdwdWNjIEdQVV9DWF9HRFNDPjsKKwkJaW9tbXVzID0gPCZhZHJlbm9fc21tdSA1PjsKKwor CQlvcGVyYXRpbmctcG9pbnRzLXYyID0gPCZnbXVfb3BwX3RhYmxlPjsKKwl9OworfTsKZGlmZiAt LWdpdCBhL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9kaXNwbGF5L21zbS9ncHUu dHh0IGIvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL2Rpc3BsYXkvbXNtL2dwdS50 eHQKaW5kZXggNGFkNWU3MGU1YzNlLi45Yzg5ZjRmZGI4Y2EgMTAwNjQ0Ci0tLSBhL0RvY3VtZW50 YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9kaXNwbGF5L21zbS9ncHUudHh0CisrKyBiL0RvY3Vt ZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9kaXNwbGF5L21zbS9ncHUudHh0CkBAIC04LDE0 ICs4LDIzIEBAIFJlcXVpcmVkIHByb3BlcnRpZXM6CiAgIHdpdGggdGhlIGNoaXAtaWQuCiAtIHJl ZzogUGh5c2ljYWwgYmFzZSBhZGRyZXNzIGFuZCBsZW5ndGggb2YgdGhlIGNvbnRyb2xsZXIncyBy ZWdpc3RlcnMuCiAtIGludGVycnVwdHM6IFRoZSBpbnRlcnJ1cHQgc2lnbmFsIGZyb20gdGhlIGdw dS4KLS0gY2xvY2tzOiBkZXZpY2UgY2xvY2tzCistIGNsb2NrczogZGV2aWNlIGNsb2NrcyAoaWYg YXBwbGljYWJsZSkKICAgU2VlIC4uL2Nsb2Nrcy9jbG9jay1iaW5kaW5ncy50eHQgZm9yIGRldGFp bHMuCi0tIGNsb2NrLW5hbWVzOiB0aGUgZm9sbG93aW5nIGNsb2NrcyBhcmUgcmVxdWlyZWQ6Cist IGNsb2NrLW5hbWVzOiB0aGUgZm9sbG93aW5nIGNsb2NrcyBhcmUgcmVxdWlyZWQgYnkgYTN4eCwg YTR4eCBhbmQgYTV4eAorICBjb3JlczoKICAgKiAiY29yZSIKICAgKiAiaWZhY2UiCiAgICogIm1l bV9pZmFjZSIKKyAgRm9yIEdNVSBhdHRhY2hlZCBkZXZpY2VzIHRoZSBHUFUgY2xvY2tzIGFyZSBu b3QgdXNlZCBhbmQgYXJlIG5vdCByZXF1aXJlZC4gVGhlCisgIGZvbGxvd2luZyBkZXZpY2VzIHNo b3VsZCBub3QgbGlzdCBjbG9ja3M6CisgICAtIHFjb20sYWRyZW5vLTYzMC4yCistIGlvbW11czog b3B0aW9uYWwgcGhhbmRsZSB0byBhbiBhZHJlbm8gaW9tbXUgaW5zdGFuY2UKKy0gb3BlcmF0aW5n LXBvaW50cy12Mjogb3B0aW9uYWwgcGhhbmRsZSB0byB0aGUgT1BQIG9wZXJhdGluZyBwb2ludHMK Ky0gcWNvbSxnbXU6IEZvciBHTVUgYXR0YWNoZWQgZGV2aWNlcyBhIHBoYW5kbGUgdG8gdGhlIEdN VSBkZXZpY2UgdGhhdCB3aWxsCisgIGNvbnRyb2wgdGhlIHBvd2VyIGZvciB0aGUgR1BVLiBBcHBs aWNhYmxlIHRhcmdldHM6CisgICAgLSBxY29tLGFkcmVuby02MzAuMgogCi1FeGFtcGxlOgorRXhh bXBsZSAzeHgvNHh4L2E1eHg6CiAKIC8gewogCS4uLgpAQCAtMzUsMyArNDQsMzAgQEAgRXhhbXBs ZToKIAkJICAgIDwmbW1jYyBNTVNTX0lNRU1fQUhCX0NMSz47CiAJfTsKIH07CisKK0V4YW1wbGUg YTZ4eCAod2l0aCBHTVUpOgorCisvIHsKKwkuLi4KKworCWdwdUA1MDAwMDAwIHsKKwkJY29tcGF0 aWJsZSA9ICJxY29tLGFkcmVuby02MzAuMiIsICJxY29tLGFkcmVubyI7CisJCSNzdHJlYW0taWQt Y2VsbHMgPSA8MTY+OworCisJCXJlZyA9IDwweDUwMDAwMDAgMHg0MDAwMD4sIDwweDUwOWUwMDAg MHgxMD47CisJCXJlZy1uYW1lcyA9ICJrZ3NsXzNkMF9yZWdfbWVtb3J5IiwgImN4X21lbSI7CisK KwkJLyoKKwkJICogTG9vayBtYSwgbm8gY2xvY2tzISBUaGUgR1BVIGNsb2NrcyBhbmQgcG93ZXIg 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(128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 82A96609C4; Tue, 18 Dec 2018 18:32:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1545157972; bh=2xZrjzhUxRf/8UD41Jynjt7ClDDaGXK825tdD93w/2A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SsldPM2I5M/cTFAYDt2JzM60lI3tCVzXbH0BLr7aFGde6iNGthabeW3xyuZLrhopU t5uwp7brLMBTdZmcG7FWI2CWVPFkMI8QIqjFm2GcRPBdLr8mku3c0i9cTt7pyl4OEi OuWUbR2ra75UpiL2v/jxj2BNqSx91Jm6Q64BzNbE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 82A96609C4 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH v7 5/6] dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings Date: Tue, 18 Dec 2018 11:32:40 -0700 Message-Id: <20181218183241.12830-6-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181218183241.12830-1-jcrouse@codeaurora.org> References: <20181218183241.12830-1-jcrouse@codeaurora.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181218_103309_852871_F1EE7587 X-CRM114-Status: GOOD ( 14.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nm@ti.com, devicetree@vger.kernel.org, rnayak@codeaurora.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, dianders@chromium.org, vireshk@kernel.org, georgi.djakov@linaro.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Update the GPU bindings and document the new bindings for the GMU device found with Adreno a6xx targets. Signed-off-by: Jordan Crouse --- v7: Updated the GMU compatible string and clarified details about when clocks can be optional on the GPU .../devicetree/bindings/display/msm/gmu.txt | 59 +++++++++++++++++++ .../devicetree/bindings/display/msm/gpu.txt | 42 ++++++++++++- 2 files changed, 98 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt b/Documentation/devicetree/bindings/display/msm/gmu.txt new file mode 100644 index 000000000000..59e6865898f2 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/gmu.txt @@ -0,0 +1,59 @@ +Qualcomm adreno/snapdragon GMU (Graphics management unit) + +The GMU is a programmable power controller for the GPU. the CPU controls the +GMU which in turn handles power controls for the GPU. + +Required properties: +- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu" + for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu" + Note that you need to list the less specific "qcom,adreno-gmu" + for generic matches and the more specific identifier to identify + the specific device. +- reg: Physical base address and length of the GMU registers. +- reg-names: Matching names for the register regions + * "gmu" + * "gmu_pdc" + * "gmu_pdc_seg" +- interrupts: The interrupt signals from the GMU. +- interrupt-names: Matching names for the interrupts + * "hfi" + * "gmu" +- clocks: phandles to the device clocks +- clock-names: Matching names for the clocks + * "gmu" + * "cxo" + * "axi" + * "mnoc" +- power-domains: should be <&clock_gpucc GPU_CX_GDSC> +- iommus: phandle to the adreno iommu +- operating-points-v2: phandle to the OPP operating points + +Example: + +/ { + ... + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; + + reg = <0x506a000 0x30000>, + <0xb280000 0x10000>, + <0xb480000 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&gpucc GPU_CX_GDSC>; + iommus = <&adreno_smmu 5>; + + operating-points-v2 = <&gmu_opp_table>; + }; +}; diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index 4ad5e70e5c3e..9c89f4fdb8ca 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -8,14 +8,23 @@ Required properties: with the chip-id. - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt signal from the gpu. -- clocks: device clocks +- clocks: device clocks (if applicable) See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required: +- clock-names: the following clocks are required by a3xx, a4xx and a5xx + cores: * "core" * "iface" * "mem_iface" + For GMU attached devices the GPU clocks are not used and are not required. The + following devices should not list clocks: + - qcom,adreno-630.2 +- iommus: optional phandle to an adreno iommu instance +- operating-points-v2: optional phandle to the OPP operating points +- qcom,gmu: For GMU attached devices a phandle to the GMU device that will + control the power for the GPU. Applicable targets: + - qcom,adreno-630.2 -Example: +Example 3xx/4xx/a5xx: / { ... @@ -35,3 +44,30 @@ Example: <&mmcc MMSS_IMEM_AHB_CLK>; }; }; + +Example a6xx (with GMU): + +/ { + ... + + gpu@5000000 { + compatible = "qcom,adreno-630.2", "qcom,adreno"; + #stream-id-cells = <16>; + + reg = <0x5000000 0x40000>, <0x509e000 0x10>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem"; + + /* + * Look ma, no clocks! The GPU clocks and power are + * controlled entirely by the GMU + */ + + interrupts = ; + + iommus = <&adreno_smmu 0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + }; +}; -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel