From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jordan Crouse Subject: [PATCH v7 6/6] arm64: dts: sdm845: Add gpu and gmu device nodes Date: Tue, 18 Dec 2018 11:32:41 -0700 Message-ID: <20181218183241.12830-7-jcrouse@codeaurora.org> References: <20181218183241.12830-1-jcrouse@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20181218183241.12830-1-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: freedreno-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Freedreno" To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: nm-l0cyMroinI0@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, rnayak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, vireshk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, georgi.djakov-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: linux-arm-msm@vger.kernel.org QWRkIHRoZSBub2RlcyB0byBkZXNjcmliZSB0aGUgQWRyZW5vIEdQVSBhbmQgR01VIGRldmljZXMu CgpTaWduZWQtb2ZmLWJ5OiBKb3JkYW4gQ3JvdXNlIDxqY3JvdXNlQGNvZGVhdXJvcmEub3JnPgot LS0KCnY3OiBVcGRhdGVkIHRoZSBHTVUgY29tcGF0aWJsZSBzdHJpbmcgYW5kIHJlbW92ZWQgaW50 ZXJydXB0LW5hbWVzCgogYXJjaC9hcm02NC9ib290L2R0cy9xY29tL3NkbTg0NS5kdHNpIHwgMTIy ICsrKysrKysrKysrKysrKysrKysrKysrKysrKwogMSBmaWxlIGNoYW5nZWQsIDEyMiBpbnNlcnRp b25zKCspCgpkaWZmIC0tZ2l0IGEvYXJjaC9hcm02NC9ib290L2R0cy9xY29tL3NkbTg0NS5kdHNp IGIvYXJjaC9hcm02NC9ib290L2R0cy9xY29tL3NkbTg0NS5kdHNpCmluZGV4IDIzM2E1ODk4ZWJj Mi4uNDc3OTAxNGU0YTA1IDEwMDY0NAotLS0gYS9hcmNoL2FybTY0L2Jvb3QvZHRzL3Fjb20vc2Rt ODQ1LmR0c2kKKysrIGIvYXJjaC9hcm02NC9ib290L2R0cy9xY29tL3NkbTg0NS5kdHNpCkBAIC0x MSw2ICsxMSw3IEBACiAjaW5jbHVkZSA8ZHQtYmluZGluZ3MvY2xvY2svcWNvbSxycG1oLmg+CiAj aW5jbHVkZSA8ZHQtYmluZGluZ3MvaW50ZXJydXB0LWNvbnRyb2xsZXIvYXJtLWdpYy5oPgogI2lu Y2x1ZGUgPGR0LWJpbmRpbmdzL3BoeS9waHktcWNvbS1xdXNiMi5oPgorI2luY2x1ZGUgPGR0LWJp bmRpbmdzL3Bvd2VyL3Fjb20tcnBtcGQuaD4KICNpbmNsdWRlIDxkdC1iaW5kaW5ncy9yZXNldC9x Y29tLHNkbTg0NS1hb3NzLmg+CiAjaW5jbHVkZSA8ZHQtYmluZGluZ3Mvc29jL3Fjb20scnBtaC1y c2MuaD4KICNpbmNsdWRlIDxkdC1iaW5kaW5ncy9jbG9jay9xY29tLGdjYy1zZG04NDUuaD4KQEAg LTEzNDksNiArMTM1MCwxMjcgQEAKIAkJCX07CiAJCX07CiAKKworCQlncHVANTAwMDAwMCB7CisJ CQljb21wYXRpYmxlID0gInFjb20sYWRyZW5vLTYzMC4yIiwgInFjb20sYWRyZW5vIjsKKwkJCSNz dHJlYW0taWQtY2VsbHMgPSA8MTY+OworCisJCQlyZWcgPSA8MHg1MDAwMDAwIDB4NDAwMDA+LCA8 MHg1MDllMDAwIDB4MTA+OworCQkJcmVnLW5hbWVzID0gImtnc2xfM2QwX3JlZ19tZW1vcnkiLCAi Y3hfbWVtIjsKKworCQkJLyoKKwkJCSAqIExvb2sgbWEsIG5vIGNsb2NrcyEgVGhlIEdQVSBjbG9j a3MgYW5kIHBvd2VyIGFyZQorCQkJICogY29udHJvbGxlZCBlbnRpcmVseSBieSB0aGUgR01VCisJ CQkgKi8KKworCQkJaW50ZXJydXB0cyA9IDxHSUNfU1BJIDMwMCBJUlFfVFlQRV9MRVZFTF9ISUdI PjsKKworCQkJaW9tbXVzID0gPCZhZHJlbm9fc21tdSAwPjsKKworCQkJb3BlcmF0aW5nLXBvaW50 cy12MiA9IDwmZ3B1X29wcF90YWJsZT47CisKKwkJCXFjb20sZ211ID0gPCZnbXU+OworCisJCQln cHVfb3BwX3RhYmxlOiBvcHAtdGFibGUgeworCQkJCWNvbXBhdGlibGUgPSAib3BlcmF0aW5nLXBv aW50cy12Mi1xY29tLWxldmVsIjsKKworCQkJCW9wcC03MTAwMDAwMDAgeworCQkJCQlvcHAtaHog PSAvYml0cy8gNjQgPDcxMDAwMDAwMD47CisJCQkJCXFjb20sbGV2ZWwgPSA8UlBNSF9SRUdVTEFU T1JfTEVWRUxfVFVSQk9fTDE+OworCQkJCX07CisKKwkJCQlvcHAtNjc1MDAwMDAwIHsKKwkJCQkJ b3BwLWh6ID0gL2JpdHMvIDY0IDw2NzUwMDAwMDA+OworCQkJCQlxY29tLGxldmVsID0gPFJQTUhf UkVHVUxBVE9SX0xFVkVMX1RVUkJPPjsKKwkJCQl9OworCisJCQkJb3BwLTU5NjAwMDAwMCB7CisJ CQkJCW9wcC1oeiA9IC9iaXRzLyA2NCA8NTk2MDAwMDAwPjsKKwkJCQkJcWNvbSxsZXZlbCA9IDxS UE1IX1JFR1VMQVRPUl9MRVZFTF9OT01fTDE+OworCQkJCX07CisKKwkJCQlvcHAtNTIwMDAwMDAw IHsKKwkJCQkJb3BwLWh6ID0gL2JpdHMvIDY0IDw1MjAwMDAwMDA+OworCQkJCQlxY29tLGxldmVs ID0gPFJQTUhfUkVHVUxBVE9SX0xFVkVMX05PTT47CisJCQkJfTsKKworCQkJCW9wcC00MTQwMDAw MDAgeworCQkJCQlvcHAtaHogPSAvYml0cy8gNjQgPDQxNDAwMDAwMD47CisJCQkJCXFjb20sbGV2 ZWwgPSA8UlBNSF9SRUdVTEFUT1JfTEVWRUxfU1ZTX0wxPjsKKwkJCQl9OworCisJCQkJb3BwLTM0 MjAwMDAwMCB7CisJCQkJCW9wcC1oeiA9IC9iaXRzLyA2NCA8MzQyMDAwMDAwPjsKKwkJCQkJcWNv bSxsZXZlbCA9IDxSUE1IX1JFR1VMQVRPUl9MRVZFTF9TVlM+OworCQkJCX07CisKKwkJCQlvcHAt MjU3MDAwMDAwIHsKKwkJCQkJb3BwLWh6ID0gL2JpdHMvIDY0IDwyNTcwMDAwMDA+OworCQkJCQlx Y29tLGxldmVsID0gPFJQTUhfUkVHVUxBVE9SX0xFVkVMX0xPV19TVlM+OworCQkJCX07CisJCQl9 OworCQl9OworCisJCWFkcmVub19zbW11OiBpb21tdUA1MDQwMDAwIHsKKwkJCWNvbXBhdGlibGUg PSAicWNvbSxzZG04NDUtc21tdS12MiIsICJxY29tLHNtbXUtdjIiOworCQkJcmVnID0gPDB4NTA0 MDAwMCAweDEwMDAwPjsKKwkJCSNpb21tdS1jZWxscyA9IDwxPjsKKwkJCSNnbG9iYWwtaW50ZXJy dXB0cyA9IDwyPjsKKwkJCWludGVycnVwdHMgPSA8R0lDX1NQSSAyMjkgSVJRX1RZUEVfTEVWRUxf SElHSD4sCisJCQkJCTxHSUNfU1BJIDIzMSBJUlFfVFlQRV9MRVZFTF9ISUdIPiwKKwkJCQkJPEdJ Q19TUEkgMzY0IElSUV9UWVBFX0VER0VfUklTSU5HPiwKKwkJCQkJPEdJQ19TUEkgMzY1IElSUV9U WVBFX0VER0VfUklTSU5HPiwKKwkJCQkJPEdJQ19TUEkgMzY2IElSUV9UWVBFX0VER0VfUklTSU5H PiwKKwkJCQkJPEdJQ19TUEkgMzY3IElSUV9UWVBFX0VER0VfUklTSU5HPiwKKwkJCQkJPEdJQ19T UEkgMzY4IElSUV9UWVBFX0VER0VfUklTSU5HPiwKKwkJCQkJPEdJQ19TUEkgMzY5IElSUV9UWVBF X0VER0VfUklTSU5HPiwKKwkJCQkJPEdJQ19TUEkgMzcwIElSUV9UWVBFX0VER0VfUklTSU5HPiwK KwkJCQkJPEdJQ19TUEkgMzcxIElSUV9UWVBFX0VER0VfUklTSU5HPjsKKwkJCWNsb2NrcyA9IDwm Z2NjIEdDQ19HUFVfTUVNTk9DX0dGWF9DTEs+LAorCQkJCTwmZ2NjIEdDQ19HUFVfQ0ZHX0FIQl9D TEs+OworCQkJY2xvY2stbmFtZXMgPSAiYnVzIiwgImlmYWNlIjsKKworCQkJcG93ZXItZG9tYWlu cyA9IDwmZ3B1Y2MgR1BVX0NYX0dEU0M+OworCQl9OworCisJCWdtdTogZ211QDUwNmEwMDAgewor CQkJY29tcGF0aWJsZT0icWNvbSxhZHJlbm8tZ211LTYzMC4yIiwgInFjb20sYWRyZW5vLWdtdSI7 CisKKwkJCXJlZyA9IDwweDUwNmEwMDAgMHgzMDAwMD4sCisJCQkJPDB4YjI4MDAwMCAweDEwMDAw PiwKKwkJCQk8MHhiNDgwMDAwIDB4MTAwMDA+OworCQkJcmVnLW5hbWVzID0gImdtdSIsICJnbXVf cGRjIiwgImdtdV9wZGNfc2VxIjsKKworCQkJaW50ZXJydXB0cyA9IDxHSUNfU1BJIDMwNCBJUlFf VFlQRV9MRVZFTF9ISUdIPiwKKwkJCSAgICAgPEdJQ19TUEkgMzA1IElSUV9UWVBFX0xFVkVMX0hJ R0g+OworCQkJaW50ZXJydXB0LW5hbWVzID0gImhmaSIsICJnbXUiOworCisJCQljbG9ja3MgPSA8 JmdwdWNjIEdQVV9DQ19DWF9HTVVfQ0xLPiwKKwkJCQk8JmdwdWNjIEdQVV9DQ19DWE9fQ0xLPiwK KwkJCQk8JmdjYyBHQ0NfRERSU1NfR1BVX0FYSV9DTEs+LAorCQkJCTwmZ2NjIEdDQ19HUFVfTUVN Tk9DX0dGWF9DTEs+OworCQkJY2xvY2stbmFtZXMgPSAiZ211IiwgImN4byIsICJheGkiLCAibWVt bm9jIjsKKworCQkJcG93ZXItZG9tYWlucyA9IDwmZ3B1Y2MgR1BVX0NYX0dEU0M+OworCQkJaW9t bXVzID0gPCZhZHJlbm9fc21tdSA1PjsKKworCQkJb3BlcmF0aW5nLXBvaW50cy12MiA9IDwmZ211 X29wcF90YWJsZT47CisKKwkJCWdtdV9vcHBfdGFibGU6IG9wcC10YWJsZSB7CisJCQkJY29tcGF0 aWJsZSA9ICJvcGVyYXRpbmctcG9pbnRzLXYyLXFjb20tbGV2ZWwiOworCisJCQkJb3BwLTQwMDAw MDAwMCB7CisJCQkJCW9wcC1oeiA9IC9iaXRzLyA2NCA8NDAwMDAwMDAwPjsKKwkJCQkJcWNvbSxs ZXZlbCA9IDxSUE1IX1JFR1VMQVRPUl9MRVZFTF9TVlM+OworCQkJCX07CisKKwkJCQlvcHAtMjAw MDAwMDAwIHsKKwkJCQkJb3BwLWh6ID0gL2JpdHMvIDY0IDwyMDAwMDAwMDA+OworCQkJCQlxY29t LGxldmVsID0gPFJQTUhfUkVHVUxBVE9SX0xFVkVMX01JTl9TVlM+OworCQkJCX07CisJCQl9Owor CQl9OworCiAJCWdwdWNjOiBjbG9jay1jb250cm9sbGVyQDUwOTAwMDAgewogCQkJY29tcGF0aWJs ZSA9ICJxY29tLHNkbTg0NS1ncHVjYyI7CiAJCQlyZWcgPSA8MHg1MDkwMDAwIDB4OTAwMD47Ci0t IAoyLjE4LjAKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f CkZyZWVkcmVubyBtYWlsaW5nIGxpc3QKRnJlZWRyZW5vQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpo dHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ZyZWVkcmVubwo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5991FC43387 for ; Tue, 18 Dec 2018 18:34:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1CF42218A2 for ; Tue, 18 Dec 2018 18:34:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="q6XSOt59"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="NVMQhoGw"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="X/lzBw/y" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1CF42218A2 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=u9IDcYX4blmzHaXBWVwNzQp4TTWEF/zcdUuAon6oiUc=; b=q6XSOt59BbQfj+DiTajexjqqIb luMqH4d6CZ2lffBD+DjyGGHmMG9bBFVlrU/QMKQRcLjeRI/8pLkk5ePa4HFzaoF7WJNoXHKeYf6Xy xcgqImxfRHqT9KLviLkTSn0CGEN2vj7uineFXsNnl8vZcc1QC/bRl4nVElSkhb+cEHEmwnJRKrSmr dE4Jj4sU4lF71VdxsqXEBdE/NHaeCnCX/iunMgVsSi1FU+mFuoiltHkfveLUTiK5MwBRqbuAFOfmO TED6USr03Gax9k34jeCp36bFW2HmSkoHQIOdPmYPW51LwQOVnhZOLRgJd8cL7iWMxXB2j6zyjpzH7 oTSX07vQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gZKCK-0000qM-Ln; Tue, 18 Dec 2018 18:34:28 +0000 Received: from smtp.codeaurora.org ([198.145.29.96]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gZKB3-000811-2w for linux-arm-kernel@lists.infradead.org; Tue, 18 Dec 2018 18:33:17 +0000 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 72C1060A71; Tue, 18 Dec 2018 18:32:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1545157978; bh=nFY1qTEU5oJHMPFCaUE8wFs6vqjJqe+jQm8wSw6Oq+4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NVMQhoGwojtKrOD+4kt6S5u/jVBokVmwoiPZwPumwqnIkUSTwQW+bA9Iedk8uXdx4 2TGjpPI5J3WLX4iBqRNYIdmpQzYiNcShTbcpyaQAJGPoMgvtlAQnwT2eqo2M2551BG 1OGlqOlhj8dy008f3t5quqFJx6r2Fg9j7s1E0ZGc= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id BA583609C3; Tue, 18 Dec 2018 18:32:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1545157974; bh=nFY1qTEU5oJHMPFCaUE8wFs6vqjJqe+jQm8wSw6Oq+4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=X/lzBw/yUxnEFpasz4LYcKftpI319lZfeTlVdJwY0kyXDsr76m0CRQ/bHnJQyKXja Mr00yCHzYXvTc4vGCbHf+nkb8NxM6FccU4851Z1J9PoHUbxN3SBwBT6Oe+Pni2wWnJ ZU0W2myfKsGKBSVqFZLVPoXDWS/Lpb/xvmJqt29A= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org BA583609C3 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH v7 6/6] arm64: dts: sdm845: Add gpu and gmu device nodes Date: Tue, 18 Dec 2018 11:32:41 -0700 Message-Id: <20181218183241.12830-7-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181218183241.12830-1-jcrouse@codeaurora.org> References: <20181218183241.12830-1-jcrouse@codeaurora.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181218_103309_784345_BA828BEC X-CRM114-Status: GOOD ( 11.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nm@ti.com, devicetree@vger.kernel.org, rnayak@codeaurora.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, dianders@chromium.org, vireshk@kernel.org, georgi.djakov@linaro.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the nodes to describe the Adreno GPU and GMU devices. Signed-off-by: Jordan Crouse --- v7: Updated the GMU compatible string and removed interrupt-names arch/arm64/boot/dts/qcom/sdm845.dtsi | 122 +++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 233a5898ebc2..4779014e4a05 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -1349,6 +1350,127 @@ }; }; + + gpu@5000000 { + compatible = "qcom,adreno-630.2", "qcom,adreno"; + #stream-id-cells = <16>; + + reg = <0x5000000 0x40000>, <0x509e000 0x10>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem"; + + /* + * Look ma, no clocks! The GPU clocks and power are + * controlled entirely by the GMU + */ + + interrupts = ; + + iommus = <&adreno_smmu 0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2-qcom-level"; + + opp-710000000 { + opp-hz = /bits/ 64 <710000000>; + qcom,level = ; + }; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + qcom,level = ; + }; + + opp-596000000 { + opp-hz = /bits/ 64 <596000000>; + qcom,level = ; + }; + + opp-520000000 { + opp-hz = /bits/ 64 <520000000>; + qcom,level = ; + }; + + opp-414000000 { + opp-hz = /bits/ 64 <414000000>; + qcom,level = ; + }; + + opp-342000000 { + opp-hz = /bits/ 64 <342000000>; + qcom,level = ; + }; + + opp-257000000 { + opp-hz = /bits/ 64 <257000000>; + qcom,level = ; + }; + }; + }; + + adreno_smmu: iommu@5040000 { + compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; + reg = <0x5040000 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "bus", "iface"; + + power-domains = <&gpucc GPU_CX_GDSC>; + }; + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; + + reg = <0x506a000 0x30000>, + <0xb280000 0x10000>, + <0xb480000 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&gpucc GPU_CX_GDSC>; + iommus = <&adreno_smmu 5>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2-qcom-level"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + qcom,level = ; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + qcom,level = ; + }; + }; + }; + gpucc: clock-controller@5090000 { compatible = "qcom,sdm845-gpucc"; reg = <0x5090000 0x9000>; -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel