Re: [RFC 15/16] drm/armada: add mmp2 support

[James Cameron <quozl@laptop.org>]

On Tue, Dec 18, 2018 at 04:37:41PM +0100, Lubomir Rintel wrote:
> This pretty much boils down to setting the LCD_CFG_SCLK_DIV register, and
> is tailored to the OLPC XO-1.75. I have no idea what are the meanings of
> most bits there, so I'm just making sure it ends up being 0x40001102.
> 
> This means that the selection of the source clock is hardwired. Apparently
> the bit 30 selects the AXI bus clock as base clock for the pixel clock.
> It is not known to me what other options are there.

I don't think so.  I'd say Display Clock 1.  See my full answer below
and Open Firmware code comment in lcd.fth;

	h# 40001102 value clkdiv  \ Display Clock 1 / 2 -> 56.93 MHz

> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> 
> ---
> Notes; perhaps James or someone else with a datasheet could help me with
> this.
> 
> I'm somewhat confused about the clock selection. The firmware contains
> this line:
> 
>   h# 00000700 value pmua-disp-clk-sel  \ PLL1 / 7 -> 113.86 MHz

In Open Firmware this is a mask of bits set in each write to offset
0x4c in the power management unit when turning LCD clocks on or off.

Name in the datasheet is PMUA_DISPLAY1_CLK_RES_CTRL.

Bits 8 through 11 are CLK_DIV_SEL, clock divider select, where 0x1 is
divide by 1, up to 0x15 (must be a typo) is divide by 15.

Bits 6 and 7 are CLK_SEL, clock select, and 0x0 is PLL1 without divider.

Given pmua-disp-clk-sel is 0x700, that's bits 8 through 10 set, so it
is configured for divide by seven.

> However, the Linux clock driver seems to consider the value of 7 to
> configure the divisor to 8, so the resulting clock would end up being
> 100 MHz. Also, the clk-of-mmp2 driver suggests PLL1 outputs 800 MHz,
> dividing that by 7 would end up being 114.29 MHz, not 113.86 MHz.

Posit PLL1 at 797.02 MHz, other comments agree, such as

dev/olpc/mmp2camera/ccic.fth: \ 797/2 (PLL1/16) / 2 -> 24.9 MHz
cforth:src/app/arm-mmp2/lcd.fth: \ PLL1 / 7 -> 113.86 MHz
src/app/arm-xo-1.75/lcdcfg.fth \ PLL1 / 7 -> 113.86 MHz
src/app/arm-mmp3-thunderstone/initdram.fth:  \  PLL1:797
src/app/arm-xo-cl4/clockset.fth:   \ PLL1:797

I've engineering notes showing recommendation to configure PLL1 for
797 MHz.

There's also the fuse configuration, which you can dump with "ok
.fuses-all".  My usual test unit is a revision C or later, and reports
910 MHz.  My notes also say that at 910 MHz the CPU is not synchronous
to the I/O buses, but that the 800 MHz or 797.02 MHz operating point
is.  I'm not sure how relevant that is, sorry.

> If the same logic was used here as Armada 510 driver uses, we'll end up
> with the divisor of 1 in LCD_CFG_SCLK_DIV and disp0_div divisor of 16.
> Would that be good also? (Do perhaps any of the bits in LCD_CFG_SCLK_DIV
> allow for a fractional divisor, allowing us to get the clock we need
> more precisely?)

Yes.  For the purposes of interoperability;

LCD_CFG_SLKC_DIV is offset 0x1a8, which is LCD_SCLK_DIV in the
datasheet.

Bits 0-7 are panel path pixel clock integer divider, and is from 2 to
255.  Open Firmware configures as 2.

Bits 8-11 are panel path mipi bit clock divider, and is from 2 to 15,
with 1 meaning bypass, and 0 meaning disabled.  Open Firmware
configures as 1.

Bits 16-27 are panel path pixel clock fraction divider.  Open Firmware
configures as 0.

Bit 28 is panel path pixel click disable (1 means disabled).

Bit 30:31 are panel path clock source select, 0 is AXI, 1 and 2 are
LCD Display clocks, and 3 is HDMI PLL clock.  Open Firmware configures
display clock 1.

> The pxa168fb driver as used on the stock OLPC software just avoids
> touching the register, preserving the value set from the firmware.
> ---
> [...]

-- 
James Cameron
http://quozl.netrek.org/
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