From: Pavel Machek <pavel@ucw.cz>
To: David Wang <davidwang@zhaoxin.com>
Cc: rjw@rjwysocki.net, mingo@redhat.com, len.brown@intel.com,
tglx@linutronix.de, hpa@zytor.com, x86@kernel.org,
linux-pm@kernel.org, linux-kernel@vger.kernel.org,
brucechang@via-alliance.com, cooperyan@zhaoxin.com,
qiyuanwang@zhaoxin.com, timguo@zhaoxin.com
Subject: Re: [PATCH v3] Optimize C3 entry on Centaur CPUs
Date: Mon, 31 Dec 2018 18:26:54 +0100 [thread overview]
Message-ID: <20181231172654.GB14092@amd> (raw)
In-Reply-To: <1545900110-2757-1-git-send-email-davidwang@zhaoxin.com>
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On Thu 2018-12-27 16:41:50, David Wang wrote:
> For new Centaur CPUs the ucode will take care of the preservation of cache coherence
> between CPU cores in C-states regardless of how deep the C-states are. So, it is not
> necessary to flush the caches in software befor entering C3. And this useless operation
> will cause performance drop for the cores which share some caches with the idling core.
>
> Signed-off-by: David Wang <davidwang@zhaoxin.com>
> Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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next prev parent reply other threads:[~2018-12-31 17:26 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-27 8:41 [PATCH v3] Optimize C3 entry on Centaur CPUs David Wang
2018-12-27 8:41 ` David Wang
2018-12-31 17:26 ` Pavel Machek [this message]
2019-04-19 18:34 ` [tip:x86/cpu] x86/power: " tip-bot for David Wang
-- strict thread matches above, loose matches on Subject: below --
2018-05-29 10:12 [PATCH v3] " David Wang
2018-05-29 10:12 ` David Wang
2018-07-20 6:38 ` Thomas Gleixner
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