diff for duplicates of <2018991.LuBz7Cl7BQ@diego> diff --git a/a/1.txt b/N1/1.txt index 72c6027..407e775 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,53 +1,50 @@ Am Dienstag, 8. November 2016, 20:31:55 schrieb Andy Yan: > Hi Heiko: ->=20 -> On 2016=E5=B9=B411=E6=9C=8804=E6=97=A5 16:00, Heiko Stuebner wrote: +> +> On 2016年11月04日 16:00, Heiko Stuebner wrote: > > Am Donnerstag, 3. November 2016, 20:40:48 CET schrieb Andy Yan: -> >> +=09gic: interrupt-controller@32010000 { -> >> +=09=09compatible =3D "arm,cortex-a15-gic"; -> >=20 -> > compatible =3D "arm,gic-400"; ? -> >=20 -> >> +=09=09interrupt-controller; -> >> +=09=09#interrupt-cells =3D <3>; -> >> +=09=09#address-cells =3D <0>; +> >> + gic: interrupt-controller@32010000 { +> >> + compatible = "arm,cortex-a15-gic"; +> > +> > compatible = "arm,gic-400"; ? +> > +> >> + interrupt-controller; +> >> + #interrupt-cells = <3>; +> >> + #address-cells = <0>; > >> + -> >> +=09=09reg =3D <0x32011000 0x1000>, -> >> +=09=09 <0x32012000 0x1000>; -> >=20 +> >> + reg = <0x32011000 0x1000>, +> >> + <0x32012000 0x1000>; +> > > > please provide all 4 register areas and also the interrupt ( ->=20 +> > I only found 2 register areas in our rockchip linux 3.10 source -> code. And haven't found the interrupt. From the arm,gic bindings, the= - +> code. And haven't found the interrupt. From the arm,gic bindings, the > interrupt property is optional. So am not sure if we > really need it here. -Devicetree is a hardware description, so it's not a factor if we "need"= - it but=20 -only if it is present in the hardware. And we really want this informat= -ion to=20 -be complete, as these additional areas are necessary if someone wants t= -o use=20 +Devicetree is a hardware description, so it's not a factor if we "need" it but +only if it is present in the hardware. And we really want this information to +be complete, as these additional areas are necessary if someone wants to use the virtualization extensions the cortext-A7 does contain. -The gic is a very standard component and the gic400 used here should de= -finitly=20 +The gic is a very standard component and the gic400 used here should definitly have those two additional areas as well as the interrupt. -I think the memory areas are pretty standard and should be for the rk11= -08: -reg =3D <0x32011000 0x1000>, +I think the memory areas are pretty standard and should be for the rk1108: +reg = <0x32011000 0x1000>, <0x32012000 0x1000>, <0x32014000 0x2000>, <0x32016000 0x2000>; -The TRM talks about 128 SPI and 3 PPI interrupts but the irq-list does = -not=20 -contain them, so this seems to be an error in the TRM, as the gic inter= -rupt=20 +The TRM talks about 128 SPI and 3 PPI interrupts but the irq-list does not +contain them, so this seems to be an error in the TRM, as the gic interrupt should be one of those PPI interrupts. Heiko + +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 928641c..43cf83f 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,74 +1,72 @@ "ref\01478175975-11779-1-git-send-email-andy.yan@rock-chips.com\0" "ref\01788707.rfxhNfegGu@phil\0" "ref\00516ad0b-bfbe-ec80-fdb6-e118dab3e758@rock-chips.com\0" - "From\0Heiko St\303\274bner <heiko@sntech.de>\0" + "ref\00516ad0b-bfbe-ec80-fdb6-e118dab3e758-TNX95d0MmH7DzftRWevZcw@public.gmane.org\0" + "From\0Heiko St\303\274bner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\0" "Subject\0Re: [PATCH 4/6] ARM: dts: add basic support for Rockchip RK1108 SOC\0" "Date\0Tue, 08 Nov 2016 14:20:17 +0100\0" - "To\0Andy Yan <andy.yan@rock-chips.com>\0" - "Cc\0elaine.zhang@rock-chips.com" - mturquette@baylibre.com - linux-rockchip@lists.infradead.org - devicetree@vger.kernel.org - robh+dt@kernel.org - mark.rutland@arm.com - linux@armlinux.org.uk - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org - " linux-kernel@vger.kernel.org\0" + "To\0Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\0" + "Cc\0elaine.zhang-TNX95d0MmH7DzftRWevZcw@public.gmane.org" + mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org + linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org + mark.rutland-5wv7dgnIgG8@public.gmane.org + linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org + linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + " linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" "\00:1\0" "b\0" "Am Dienstag, 8. November 2016, 20:31:55 schrieb Andy Yan:\n" "> Hi Heiko:\n" - ">=20\n" - "> On 2016=E5=B9=B411=E6=9C=8804=E6=97=A5 16:00, Heiko Stuebner wrote:\n" + "> \n" + "> On 2016\345\271\26411\346\234\21004\346\227\245 16:00, Heiko Stuebner wrote:\n" "> > Am Donnerstag, 3. November 2016, 20:40:48 CET schrieb Andy Yan:\n" "\n" - "> >> +=09gic: interrupt-controller@32010000 {\n" - "> >> +=09=09compatible =3D \"arm,cortex-a15-gic\";\n" - "> >=20\n" - "> > compatible =3D \"arm,gic-400\"; ?\n" - "> >=20\n" - "> >> +=09=09interrupt-controller;\n" - "> >> +=09=09#interrupt-cells =3D <3>;\n" - "> >> +=09=09#address-cells =3D <0>;\n" + "> >> +\tgic: interrupt-controller@32010000 {\n" + "> >> +\t\tcompatible = \"arm,cortex-a15-gic\";\n" + "> > \n" + "> > compatible = \"arm,gic-400\"; ?\n" + "> > \n" + "> >> +\t\tinterrupt-controller;\n" + "> >> +\t\t#interrupt-cells = <3>;\n" + "> >> +\t\t#address-cells = <0>;\n" "> >> +\n" - "> >> +=09=09reg =3D <0x32011000 0x1000>,\n" - "> >> +=09=09 <0x32012000 0x1000>;\n" - "> >=20\n" + "> >> +\t\treg = <0x32011000 0x1000>,\n" + "> >> +\t\t <0x32012000 0x1000>;\n" + "> > \n" "> > please provide all 4 register areas and also the interrupt (\n" - ">=20\n" + "> \n" "> I only found 2 register areas in our rockchip linux 3.10 source\n" - "> code. And haven't found the interrupt. From the arm,gic bindings, the=\n" - "\n" + "> code. And haven't found the interrupt. From the arm,gic bindings, the\n" "> interrupt property is optional. So am not sure if we\n" "> really need it here.\n" "\n" - "Devicetree is a hardware description, so it's not a factor if we \"need\"=\n" - " it but=20\n" - "only if it is present in the hardware. And we really want this informat=\n" - "ion to=20\n" - "be complete, as these additional areas are necessary if someone wants t=\n" - "o use=20\n" + "Devicetree is a hardware description, so it's not a factor if we \"need\" it but \n" + "only if it is present in the hardware. And we really want this information to \n" + "be complete, as these additional areas are necessary if someone wants to use \n" "the virtualization extensions the cortext-A7 does contain.\n" "\n" - "The gic is a very standard component and the gic400 used here should de=\n" - "finitly=20\n" + "The gic is a very standard component and the gic400 used here should definitly \n" "have those two additional areas as well as the interrupt.\n" "\n" - "I think the memory areas are pretty standard and should be for the rk11=\n" - "08:\n" - "reg =3D <0x32011000 0x1000>,\n" + "I think the memory areas are pretty standard and should be for the rk1108:\n" + "reg = <0x32011000 0x1000>,\n" " <0x32012000 0x1000>,\n" " <0x32014000 0x2000>,\n" " <0x32016000 0x2000>;\n" "\n" - "The TRM talks about 128 SPI and 3 PPI interrupts but the irq-list does =\n" - "not=20\n" - "contain them, so this seems to be an error in the TRM, as the gic inter=\n" - "rupt=20\n" + "The TRM talks about 128 SPI and 3 PPI interrupts but the irq-list does not \n" + "contain them, so this seems to be an error in the TRM, as the gic interrupt \n" "should be one of those PPI interrupts.\n" "\n" "\n" - Heiko + "Heiko\n" + "\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -44dc376b9f1c90b5b0a715111df8db30b17b10664f4458d2204b89c306e6727b +23fd6e79a519902c0d0c2695c985489c000982e76aac07f7b035a8c28184b0a1
diff --git a/a/1.txt b/N2/1.txt index 72c6027..24abba5 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,52 +1,44 @@ Am Dienstag, 8. November 2016, 20:31:55 schrieb Andy Yan: > Hi Heiko: ->=20 -> On 2016=E5=B9=B411=E6=9C=8804=E6=97=A5 16:00, Heiko Stuebner wrote: +> +> On 2016?11?04? 16:00, Heiko Stuebner wrote: > > Am Donnerstag, 3. November 2016, 20:40:48 CET schrieb Andy Yan: -> >> +=09gic: interrupt-controller@32010000 { -> >> +=09=09compatible =3D "arm,cortex-a15-gic"; -> >=20 -> > compatible =3D "arm,gic-400"; ? -> >=20 -> >> +=09=09interrupt-controller; -> >> +=09=09#interrupt-cells =3D <3>; -> >> +=09=09#address-cells =3D <0>; +> >> + gic: interrupt-controller at 32010000 { +> >> + compatible = "arm,cortex-a15-gic"; +> > +> > compatible = "arm,gic-400"; ? +> > +> >> + interrupt-controller; +> >> + #interrupt-cells = <3>; +> >> + #address-cells = <0>; > >> + -> >> +=09=09reg =3D <0x32011000 0x1000>, -> >> +=09=09 <0x32012000 0x1000>; -> >=20 +> >> + reg = <0x32011000 0x1000>, +> >> + <0x32012000 0x1000>; +> > > > please provide all 4 register areas and also the interrupt ( ->=20 +> > I only found 2 register areas in our rockchip linux 3.10 source -> code. And haven't found the interrupt. From the arm,gic bindings, the= - +> code. And haven't found the interrupt. From the arm,gic bindings, the > interrupt property is optional. So am not sure if we > really need it here. -Devicetree is a hardware description, so it's not a factor if we "need"= - it but=20 -only if it is present in the hardware. And we really want this informat= -ion to=20 -be complete, as these additional areas are necessary if someone wants t= -o use=20 +Devicetree is a hardware description, so it's not a factor if we "need" it but +only if it is present in the hardware. And we really want this information to +be complete, as these additional areas are necessary if someone wants to use the virtualization extensions the cortext-A7 does contain. -The gic is a very standard component and the gic400 used here should de= -finitly=20 +The gic is a very standard component and the gic400 used here should definitly have those two additional areas as well as the interrupt. -I think the memory areas are pretty standard and should be for the rk11= -08: -reg =3D <0x32011000 0x1000>, +I think the memory areas are pretty standard and should be for the rk1108: +reg = <0x32011000 0x1000>, <0x32012000 0x1000>, <0x32014000 0x2000>, <0x32016000 0x2000>; -The TRM talks about 128 SPI and 3 PPI interrupts but the irq-list does = -not=20 -contain them, so this seems to be an error in the TRM, as the gic inter= -rupt=20 +The TRM talks about 128 SPI and 3 PPI interrupts but the irq-list does not +contain them, so this seems to be an error in the TRM, as the gic interrupt should be one of those PPI interrupts. diff --git a/a/content_digest b/N2/content_digest index 928641c..fe4d5e5 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,74 +1,56 @@ "ref\01478175975-11779-1-git-send-email-andy.yan@rock-chips.com\0" "ref\01788707.rfxhNfegGu@phil\0" "ref\00516ad0b-bfbe-ec80-fdb6-e118dab3e758@rock-chips.com\0" - "From\0Heiko St\303\274bner <heiko@sntech.de>\0" - "Subject\0Re: [PATCH 4/6] ARM: dts: add basic support for Rockchip RK1108 SOC\0" + "From\0heiko@sntech.de (Heiko St\303\274bner)\0" + "Subject\0[PATCH 4/6] ARM: dts: add basic support for Rockchip RK1108 SOC\0" "Date\0Tue, 08 Nov 2016 14:20:17 +0100\0" - "To\0Andy Yan <andy.yan@rock-chips.com>\0" - "Cc\0elaine.zhang@rock-chips.com" - mturquette@baylibre.com - linux-rockchip@lists.infradead.org - devicetree@vger.kernel.org - robh+dt@kernel.org - mark.rutland@arm.com - linux@armlinux.org.uk - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org - " linux-kernel@vger.kernel.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Am Dienstag, 8. November 2016, 20:31:55 schrieb Andy Yan:\n" "> Hi Heiko:\n" - ">=20\n" - "> On 2016=E5=B9=B411=E6=9C=8804=E6=97=A5 16:00, Heiko Stuebner wrote:\n" + "> \n" + "> On 2016?11?04? 16:00, Heiko Stuebner wrote:\n" "> > Am Donnerstag, 3. November 2016, 20:40:48 CET schrieb Andy Yan:\n" "\n" - "> >> +=09gic: interrupt-controller@32010000 {\n" - "> >> +=09=09compatible =3D \"arm,cortex-a15-gic\";\n" - "> >=20\n" - "> > compatible =3D \"arm,gic-400\"; ?\n" - "> >=20\n" - "> >> +=09=09interrupt-controller;\n" - "> >> +=09=09#interrupt-cells =3D <3>;\n" - "> >> +=09=09#address-cells =3D <0>;\n" + "> >> +\tgic: interrupt-controller at 32010000 {\n" + "> >> +\t\tcompatible = \"arm,cortex-a15-gic\";\n" + "> > \n" + "> > compatible = \"arm,gic-400\"; ?\n" + "> > \n" + "> >> +\t\tinterrupt-controller;\n" + "> >> +\t\t#interrupt-cells = <3>;\n" + "> >> +\t\t#address-cells = <0>;\n" "> >> +\n" - "> >> +=09=09reg =3D <0x32011000 0x1000>,\n" - "> >> +=09=09 <0x32012000 0x1000>;\n" - "> >=20\n" + "> >> +\t\treg = <0x32011000 0x1000>,\n" + "> >> +\t\t <0x32012000 0x1000>;\n" + "> > \n" "> > please provide all 4 register areas and also the interrupt (\n" - ">=20\n" + "> \n" "> I only found 2 register areas in our rockchip linux 3.10 source\n" - "> code. And haven't found the interrupt. From the arm,gic bindings, the=\n" - "\n" + "> code. And haven't found the interrupt. From the arm,gic bindings, the\n" "> interrupt property is optional. So am not sure if we\n" "> really need it here.\n" "\n" - "Devicetree is a hardware description, so it's not a factor if we \"need\"=\n" - " it but=20\n" - "only if it is present in the hardware. And we really want this informat=\n" - "ion to=20\n" - "be complete, as these additional areas are necessary if someone wants t=\n" - "o use=20\n" + "Devicetree is a hardware description, so it's not a factor if we \"need\" it but \n" + "only if it is present in the hardware. And we really want this information to \n" + "be complete, as these additional areas are necessary if someone wants to use \n" "the virtualization extensions the cortext-A7 does contain.\n" "\n" - "The gic is a very standard component and the gic400 used here should de=\n" - "finitly=20\n" + "The gic is a very standard component and the gic400 used here should definitly \n" "have those two additional areas as well as the interrupt.\n" "\n" - "I think the memory areas are pretty standard and should be for the rk11=\n" - "08:\n" - "reg =3D <0x32011000 0x1000>,\n" + "I think the memory areas are pretty standard and should be for the rk1108:\n" + "reg = <0x32011000 0x1000>,\n" " <0x32012000 0x1000>,\n" " <0x32014000 0x2000>,\n" " <0x32016000 0x2000>;\n" "\n" - "The TRM talks about 128 SPI and 3 PPI interrupts but the irq-list does =\n" - "not=20\n" - "contain them, so this seems to be an error in the TRM, as the gic inter=\n" - "rupt=20\n" + "The TRM talks about 128 SPI and 3 PPI interrupts but the irq-list does not \n" + "contain them, so this seems to be an error in the TRM, as the gic interrupt \n" "should be one of those PPI interrupts.\n" "\n" "\n" Heiko -44dc376b9f1c90b5b0a715111df8db30b17b10664f4458d2204b89c306e6727b +32c5302999c52719f4f0899db0d6f0610dab429d64635410d3bb514b15ba3074
diff --git a/a/1.txt b/N3/1.txt index 72c6027..7d9a0de 100644 --- a/a/1.txt +++ b/N3/1.txt @@ -1,52 +1,44 @@ Am Dienstag, 8. November 2016, 20:31:55 schrieb Andy Yan: > Hi Heiko: ->=20 -> On 2016=E5=B9=B411=E6=9C=8804=E6=97=A5 16:00, Heiko Stuebner wrote: +> +> On 2016年11月04日 16:00, Heiko Stuebner wrote: > > Am Donnerstag, 3. November 2016, 20:40:48 CET schrieb Andy Yan: -> >> +=09gic: interrupt-controller@32010000 { -> >> +=09=09compatible =3D "arm,cortex-a15-gic"; -> >=20 -> > compatible =3D "arm,gic-400"; ? -> >=20 -> >> +=09=09interrupt-controller; -> >> +=09=09#interrupt-cells =3D <3>; -> >> +=09=09#address-cells =3D <0>; +> >> + gic: interrupt-controller@32010000 { +> >> + compatible = "arm,cortex-a15-gic"; +> > +> > compatible = "arm,gic-400"; ? +> > +> >> + interrupt-controller; +> >> + #interrupt-cells = <3>; +> >> + #address-cells = <0>; > >> + -> >> +=09=09reg =3D <0x32011000 0x1000>, -> >> +=09=09 <0x32012000 0x1000>; -> >=20 +> >> + reg = <0x32011000 0x1000>, +> >> + <0x32012000 0x1000>; +> > > > please provide all 4 register areas and also the interrupt ( ->=20 +> > I only found 2 register areas in our rockchip linux 3.10 source -> code. And haven't found the interrupt. From the arm,gic bindings, the= - +> code. And haven't found the interrupt. From the arm,gic bindings, the > interrupt property is optional. So am not sure if we > really need it here. -Devicetree is a hardware description, so it's not a factor if we "need"= - it but=20 -only if it is present in the hardware. And we really want this informat= -ion to=20 -be complete, as these additional areas are necessary if someone wants t= -o use=20 +Devicetree is a hardware description, so it's not a factor if we "need" it but +only if it is present in the hardware. And we really want this information to +be complete, as these additional areas are necessary if someone wants to use the virtualization extensions the cortext-A7 does contain. -The gic is a very standard component and the gic400 used here should de= -finitly=20 +The gic is a very standard component and the gic400 used here should definitly have those two additional areas as well as the interrupt. -I think the memory areas are pretty standard and should be for the rk11= -08: -reg =3D <0x32011000 0x1000>, +I think the memory areas are pretty standard and should be for the rk1108: +reg = <0x32011000 0x1000>, <0x32012000 0x1000>, <0x32014000 0x2000>, <0x32016000 0x2000>; -The TRM talks about 128 SPI and 3 PPI interrupts but the irq-list does = -not=20 -contain them, so this seems to be an error in the TRM, as the gic inter= -rupt=20 +The TRM talks about 128 SPI and 3 PPI interrupts but the irq-list does not +contain them, so this seems to be an error in the TRM, as the gic interrupt should be one of those PPI interrupts. diff --git a/a/content_digest b/N3/content_digest index 928641c..d79b1d5 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -19,56 +19,48 @@ "b\0" "Am Dienstag, 8. November 2016, 20:31:55 schrieb Andy Yan:\n" "> Hi Heiko:\n" - ">=20\n" - "> On 2016=E5=B9=B411=E6=9C=8804=E6=97=A5 16:00, Heiko Stuebner wrote:\n" + "> \n" + "> On 2016\345\271\26411\346\234\21004\346\227\245 16:00, Heiko Stuebner wrote:\n" "> > Am Donnerstag, 3. November 2016, 20:40:48 CET schrieb Andy Yan:\n" "\n" - "> >> +=09gic: interrupt-controller@32010000 {\n" - "> >> +=09=09compatible =3D \"arm,cortex-a15-gic\";\n" - "> >=20\n" - "> > compatible =3D \"arm,gic-400\"; ?\n" - "> >=20\n" - "> >> +=09=09interrupt-controller;\n" - "> >> +=09=09#interrupt-cells =3D <3>;\n" - "> >> +=09=09#address-cells =3D <0>;\n" + "> >> +\tgic: interrupt-controller@32010000 {\n" + "> >> +\t\tcompatible = \"arm,cortex-a15-gic\";\n" + "> > \n" + "> > compatible = \"arm,gic-400\"; ?\n" + "> > \n" + "> >> +\t\tinterrupt-controller;\n" + "> >> +\t\t#interrupt-cells = <3>;\n" + "> >> +\t\t#address-cells = <0>;\n" "> >> +\n" - "> >> +=09=09reg =3D <0x32011000 0x1000>,\n" - "> >> +=09=09 <0x32012000 0x1000>;\n" - "> >=20\n" + "> >> +\t\treg = <0x32011000 0x1000>,\n" + "> >> +\t\t <0x32012000 0x1000>;\n" + "> > \n" "> > please provide all 4 register areas and also the interrupt (\n" - ">=20\n" + "> \n" "> I only found 2 register areas in our rockchip linux 3.10 source\n" - "> code. And haven't found the interrupt. From the arm,gic bindings, the=\n" - "\n" + "> code. And haven't found the interrupt. From the arm,gic bindings, the\n" "> interrupt property is optional. So am not sure if we\n" "> really need it here.\n" "\n" - "Devicetree is a hardware description, so it's not a factor if we \"need\"=\n" - " it but=20\n" - "only if it is present in the hardware. And we really want this informat=\n" - "ion to=20\n" - "be complete, as these additional areas are necessary if someone wants t=\n" - "o use=20\n" + "Devicetree is a hardware description, so it's not a factor if we \"need\" it but \n" + "only if it is present in the hardware. And we really want this information to \n" + "be complete, as these additional areas are necessary if someone wants to use \n" "the virtualization extensions the cortext-A7 does contain.\n" "\n" - "The gic is a very standard component and the gic400 used here should de=\n" - "finitly=20\n" + "The gic is a very standard component and the gic400 used here should definitly \n" "have those two additional areas as well as the interrupt.\n" "\n" - "I think the memory areas are pretty standard and should be for the rk11=\n" - "08:\n" - "reg =3D <0x32011000 0x1000>,\n" + "I think the memory areas are pretty standard and should be for the rk1108:\n" + "reg = <0x32011000 0x1000>,\n" " <0x32012000 0x1000>,\n" " <0x32014000 0x2000>,\n" " <0x32016000 0x2000>;\n" "\n" - "The TRM talks about 128 SPI and 3 PPI interrupts but the irq-list does =\n" - "not=20\n" - "contain them, so this seems to be an error in the TRM, as the gic inter=\n" - "rupt=20\n" + "The TRM talks about 128 SPI and 3 PPI interrupts but the irq-list does not \n" + "contain them, so this seems to be an error in the TRM, as the gic interrupt \n" "should be one of those PPI interrupts.\n" "\n" "\n" Heiko -44dc376b9f1c90b5b0a715111df8db30b17b10664f4458d2204b89c306e6727b +e31c72264546f947bc127658e41a1660c700ab504dc536445b10ac10d998607f
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