From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Andy Yan Cc: elaine.zhang@rock-chips.com, mturquette@baylibre.com, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 4/6] ARM: dts: add basic support for Rockchip RK1108 SOC Date: Tue, 08 Nov 2016 14:20:17 +0100 Message-ID: <2018991.LuBz7Cl7BQ@diego> In-Reply-To: <0516ad0b-bfbe-ec80-fdb6-e118dab3e758@rock-chips.com> References: <1478175975-11779-1-git-send-email-andy.yan@rock-chips.com> <1788707.rfxhNfegGu@phil> <0516ad0b-bfbe-ec80-fdb6-e118dab3e758@rock-chips.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" List-ID: Am Dienstag, 8. November 2016, 20:31:55 schrieb Andy Yan: > Hi Heiko: >=20 > On 2016=E5=B9=B411=E6=9C=8804=E6=97=A5 16:00, Heiko Stuebner wrote: > > Am Donnerstag, 3. November 2016, 20:40:48 CET schrieb Andy Yan: > >> +=09gic: interrupt-controller@32010000 { > >> +=09=09compatible =3D "arm,cortex-a15-gic"; > >=20 > > compatible =3D "arm,gic-400"; ? > >=20 > >> +=09=09interrupt-controller; > >> +=09=09#interrupt-cells =3D <3>; > >> +=09=09#address-cells =3D <0>; > >> + > >> +=09=09reg =3D <0x32011000 0x1000>, > >> +=09=09 <0x32012000 0x1000>; > >=20 > > please provide all 4 register areas and also the interrupt ( >=20 > I only found 2 register areas in our rockchip linux 3.10 source > code. And haven't found the interrupt. From the arm,gic bindings, the= > interrupt property is optional. So am not sure if we > really need it here. Devicetree is a hardware description, so it's not a factor if we "need"= it but=20 only if it is present in the hardware. And we really want this informat= ion to=20 be complete, as these additional areas are necessary if someone wants t= o use=20 the virtualization extensions the cortext-A7 does contain. The gic is a very standard component and the gic400 used here should de= finitly=20 have those two additional areas as well as the interrupt. I think the memory areas are pretty standard and should be for the rk11= 08: reg =3D <0x32011000 0x1000>, <0x32012000 0x1000>, <0x32014000 0x2000>, <0x32016000 0x2000>; The TRM talks about 128 SPI and 3 PPI interrupts but the irq-list does = not=20 contain them, so this seems to be an error in the TRM, as the gic inter= rupt=20 should be one of those PPI interrupts. Heiko From mboxrd@z Thu Jan 1 00:00:00 1970 From: Heiko =?ISO-8859-1?Q?St=FCbner?= Subject: Re: [PATCH 4/6] ARM: dts: add basic support for Rockchip RK1108 SOC Date: Tue, 08 Nov 2016 14:20:17 +0100 Message-ID: <2018991.LuBz7Cl7BQ@diego> References: <1478175975-11779-1-git-send-email-andy.yan@rock-chips.com> <1788707.rfxhNfegGu@phil> <0516ad0b-bfbe-ec80-fdb6-e118dab3e758@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Return-path: In-Reply-To: <0516ad0b-bfbe-ec80-fdb6-e118dab3e758-TNX95d0MmH7DzftRWevZcw@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Andy Yan Cc: elaine.zhang-TNX95d0MmH7DzftRWevZcw@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-rockchip.vger.kernel.org Am Dienstag, 8. November 2016, 20:31:55 schrieb Andy Yan: > Hi Heiko: > > On 2016年11月04日 16:00, Heiko Stuebner wrote: > > Am Donnerstag, 3. November 2016, 20:40:48 CET schrieb Andy Yan: > >> + gic: interrupt-controller@32010000 { > >> + compatible = "arm,cortex-a15-gic"; > > > > compatible = "arm,gic-400"; ? > > > >> + interrupt-controller; > >> + #interrupt-cells = <3>; > >> + #address-cells = <0>; > >> + > >> + reg = <0x32011000 0x1000>, > >> + <0x32012000 0x1000>; > > > > please provide all 4 register areas and also the interrupt ( > > I only found 2 register areas in our rockchip linux 3.10 source > code. And haven't found the interrupt. From the arm,gic bindings, the > interrupt property is optional. So am not sure if we > really need it here. Devicetree is a hardware description, so it's not a factor if we "need" it but only if it is present in the hardware. And we really want this information to be complete, as these additional areas are necessary if someone wants to use the virtualization extensions the cortext-A7 does contain. The gic is a very standard component and the gic400 used here should definitly have those two additional areas as well as the interrupt. I think the memory areas are pretty standard and should be for the rk1108: reg = <0x32011000 0x1000>, <0x32012000 0x1000>, <0x32014000 0x2000>, <0x32016000 0x2000>; The TRM talks about 128 SPI and 3 PPI interrupts but the irq-list does not contain them, so this seems to be an error in the TRM, as the gic interrupt should be one of those PPI interrupts. Heiko -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: heiko@sntech.de (Heiko =?ISO-8859-1?Q?St=FCbner?=) Date: Tue, 08 Nov 2016 14:20:17 +0100 Subject: [PATCH 4/6] ARM: dts: add basic support for Rockchip RK1108 SOC In-Reply-To: <0516ad0b-bfbe-ec80-fdb6-e118dab3e758@rock-chips.com> References: <1478175975-11779-1-git-send-email-andy.yan@rock-chips.com> <1788707.rfxhNfegGu@phil> <0516ad0b-bfbe-ec80-fdb6-e118dab3e758@rock-chips.com> Message-ID: <2018991.LuBz7Cl7BQ@diego> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Am Dienstag, 8. November 2016, 20:31:55 schrieb Andy Yan: > Hi Heiko: > > On 2016?11?04? 16:00, Heiko Stuebner wrote: > > Am Donnerstag, 3. November 2016, 20:40:48 CET schrieb Andy Yan: > >> + gic: interrupt-controller at 32010000 { > >> + compatible = "arm,cortex-a15-gic"; > > > > compatible = "arm,gic-400"; ? > > > >> + interrupt-controller; > >> + #interrupt-cells = <3>; > >> + #address-cells = <0>; > >> + > >> + reg = <0x32011000 0x1000>, > >> + <0x32012000 0x1000>; > > > > please provide all 4 register areas and also the interrupt ( > > I only found 2 register areas in our rockchip linux 3.10 source > code. And haven't found the interrupt. From the arm,gic bindings, the > interrupt property is optional. So am not sure if we > really need it here. Devicetree is a hardware description, so it's not a factor if we "need" it but only if it is present in the hardware. And we really want this information to be complete, as these additional areas are necessary if someone wants to use the virtualization extensions the cortext-A7 does contain. The gic is a very standard component and the gic400 used here should definitly have those two additional areas as well as the interrupt. I think the memory areas are pretty standard and should be for the rk1108: reg = <0x32011000 0x1000>, <0x32012000 0x1000>, <0x32014000 0x2000>, <0x32016000 0x2000>; The TRM talks about 128 SPI and 3 PPI interrupts but the irq-list does not contain them, so this seems to be an error in the TRM, as the gic interrupt should be one of those PPI interrupts. Heiko From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751496AbcKHNVC convert rfc822-to-8bit (ORCPT ); Tue, 8 Nov 2016 08:21:02 -0500 Received: from gloria.sntech.de ([95.129.55.99]:43003 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750928AbcKHNVA (ORCPT ); Tue, 8 Nov 2016 08:21:00 -0500 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Andy Yan Cc: elaine.zhang@rock-chips.com, mturquette@baylibre.com, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 4/6] ARM: dts: add basic support for Rockchip RK1108 SOC Date: Tue, 08 Nov 2016 14:20:17 +0100 Message-ID: <2018991.LuBz7Cl7BQ@diego> User-Agent: KMail/4.14.10 (Linux/4.6.0-1-amd64; KDE/4.14.22; x86_64; ; ) In-Reply-To: <0516ad0b-bfbe-ec80-fdb6-e118dab3e758@rock-chips.com> References: <1478175975-11779-1-git-send-email-andy.yan@rock-chips.com> <1788707.rfxhNfegGu@phil> <0516ad0b-bfbe-ec80-fdb6-e118dab3e758@rock-chips.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="utf-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Dienstag, 8. November 2016, 20:31:55 schrieb Andy Yan: > Hi Heiko: > > On 2016年11月04日 16:00, Heiko Stuebner wrote: > > Am Donnerstag, 3. November 2016, 20:40:48 CET schrieb Andy Yan: > >> + gic: interrupt-controller@32010000 { > >> + compatible = "arm,cortex-a15-gic"; > > > > compatible = "arm,gic-400"; ? > > > >> + interrupt-controller; > >> + #interrupt-cells = <3>; > >> + #address-cells = <0>; > >> + > >> + reg = <0x32011000 0x1000>, > >> + <0x32012000 0x1000>; > > > > please provide all 4 register areas and also the interrupt ( > > I only found 2 register areas in our rockchip linux 3.10 source > code. And haven't found the interrupt. From the arm,gic bindings, the > interrupt property is optional. So am not sure if we > really need it here. Devicetree is a hardware description, so it's not a factor if we "need" it but only if it is present in the hardware. And we really want this information to be complete, as these additional areas are necessary if someone wants to use the virtualization extensions the cortext-A7 does contain. The gic is a very standard component and the gic400 used here should definitly have those two additional areas as well as the interrupt. I think the memory areas are pretty standard and should be for the rk1108: reg = <0x32011000 0x1000>, <0x32012000 0x1000>, <0x32014000 0x2000>, <0x32016000 0x2000>; The TRM talks about 128 SPI and 3 PPI interrupts but the irq-list does not contain them, so this seems to be an error in the TRM, as the gic interrupt should be one of those PPI interrupts. Heiko