[MODERATED] Re: [PATCH v3 00/32] MDSv3 12

[Andi Kleen <ak@linux.intel.com>]

> > I don't know what parts of Intel you're talking with, but the parts
> > I talk with say that it's likely some CPUs won't be able to do the
> > microcode update for VERW.
> 
> Right. And they say that because nobody cares.

There are two different cases:

- Some old CPUs won't get any support. That's the "nobody cares" 
case. I already don't support those in the patch (e.g. pre Nehalem)

- Some newer CPUs where people care and which are widely used, but they ran
out of space for the patch.  So they would like to, but can't. That's the cases
I'm trying to handle.

> I will not take that crazy per-microarchitecture software sequence
> THAT DOESN'T EVEN WORK. Even on the micro-architectures it is designed
> for, virtualization and SMM break it.

Virtualization works, as long as the Hypervisor supports it. I fixed
KVM to do so (it's in the patchkit). Basically it needs to always
flush on entry if VERW is not exposed to the guest. This ensures
that even if the sequence is interrupted, a clear happens anyways.

SMM is a problem on CPUs without microcode update. It could be handled
by a BIOS update (and some vendors might do that). 
However SMM is quite rare and normally not user controllable (with the 
recent fixes we did for retpoline) so I think it falls into your
"theoretical only / uninteresting" cases bucket.

Does that change anything in your opinion?

-Andi