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From: Jim Qu <Jim.Qu-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Jim Qu <Jim.Qu-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 2/6] drm/amdgpu: add BACO interfaces in pm and hwmgr function table
Date: Thu, 10 Jan 2019 12:09:21 +0800	[thread overview]
Message-ID: <20190110040925.25533-3-Jim.Qu@amd.com> (raw)
In-Reply-To: <20190110040925.25533-1-Jim.Qu-5C7GfCeVMHo@public.gmane.org>

Change-Id: I55e58b4627e6d5935dbe56657bef65f37b2a39b3
Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
 drivers/gpu/drm/amd/include/kgd_pp_interface.h | 3 +++
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h      | 8 ++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 789c4f288485..a2ea4c933360 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -281,6 +281,9 @@ struct amd_pm_funcs {
 	int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
 	int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
 	int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
+	int (*get_asic_baco_capability)(void *handle, bool *cap);
+	int (*get_asic_baco_state)(void *handle, int *state);
+	int (*set_asic_baco_state)(void *handle, int state);
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index be4f87aed99c..577cec90aef1 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -47,6 +47,11 @@ enum DISPLAY_GAP {
 };
 typedef enum DISPLAY_GAP DISPLAY_GAP;
 
+enum BACO_STATE {
+	BACO_STATE_OUT = 0,
+	BACO_STATE_IN,
+};
+
 struct vi_dpm_level {
 	bool enabled;
 	uint32_t value;
@@ -333,6 +338,9 @@ struct pp_hwmgr_func {
 	int (*enable_mgpu_fan_boost)(struct pp_hwmgr *hwmgr);
 	int (*set_hard_min_dcefclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
 	int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
+	int (*get_asic_baco_capability)(struct pp_hwmgr *hwmgr, bool *cap);
+	int (*get_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
+	int (*set_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
 };
 
 struct pp_table_func {
-- 
2.17.1

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  parent reply	other threads:[~2019-01-10  4:09 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-10  4:09 [PATCH 0/6] Enable BACO function for VGf10 Jim Qu
     [not found] ` <20190110040925.25533-1-Jim.Qu-5C7GfCeVMHo@public.gmane.org>
2019-01-10  4:09   ` [PATCH 1/6] drm/amdgpu: update nbio v6.1 register/master to support BACO Jim Qu
2019-01-10  4:09   ` Jim Qu [this message]
2019-01-10  4:09   ` [PATCH 3/6] drm/amdpgu: add common functions for BACO feature in PP Jim Qu
2019-01-10  4:09   ` [PATCH 4/6] drm/amdgpu: add BACO interfaces for vega10 Jim Qu
2019-01-10  4:09   ` [PATCH 5/6] drm/amdgpu: expose BACO interfaces to upper level from PP Jim Qu
2019-01-10  4:09   ` [PATCH 6/6] drm/amdgpu: use BACO reset if platform support Jim Qu

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