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From: Jim Qu <Jim.Qu-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Jim Qu <Jim.Qu-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 5/5] drm/amdgpu: use BACO reset on vega20 if platform support
Date: Fri, 11 Jan 2019 11:19:50 +0800	[thread overview]
Message-ID: <20190111031950.32475-6-Jim.Qu@amd.com> (raw)
In-Reply-To: <20190111031950.32475-1-Jim.Qu-5C7GfCeVMHo@public.gmane.org>

Change-Id: I531fa83ccf4abf593194afd6ff0702ba1393d6c7
Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index ece6fca476d4..baf90380df6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -462,6 +462,7 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
 
 	switch (adev->asic_type) {
 	case CHIP_VEGA10:
+	case CHIP_VEGA20:
 		soc15_asic_get_baco_capability(adev, &baco_reset);
 		break;
 	default:
-- 
2.17.1

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      parent reply	other threads:[~2019-01-11  3:19 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-11  3:19 [PATCH 0/5] Enable BACO function on VG20 Jim Qu
     [not found] ` <20190111031950.32475-1-Jim.Qu-5C7GfCeVMHo@public.gmane.org>
2019-01-11  3:19   ` [PATCH 1/5] drm/amdgpu: update NBIO v7.4 to support BACO Jim Qu
2019-01-11  3:19   ` [PATCH 2/5] drm/amdgpu: also include NBIO v7.4 register mask header Jim Qu
2019-01-11  3:19   ` [PATCH 3/5] drm/amdgpu: update THM IP register header to support BACO Jim Qu
2019-01-11  3:19   ` [PATCH 4/5] drm/amdgpu/powerper: add vega20 BACO functins Jim Qu
2019-01-11  3:19   ` Jim Qu [this message]

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