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From: Thierry Reding <thierry.reding@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: linux-tegra@vger.kernel.org, Dmitry Osipenko <digetx@gmail.com>,
	dri-devel@lists.freedesktop.org,
	Mikko Perttunen <mperttunen@nvidia.com>
Subject: [PATCH v2 02/13] gpu: host1x: Program the channel stream ID
Date: Thu, 24 Jan 2019 19:02:43 +0100	[thread overview]
Message-ID: <20190124180254.20080-3-thierry.reding@gmail.com> (raw)
In-Reply-To: <20190124180254.20080-1-thierry.reding@gmail.com>

From: Thierry Reding <treding@nvidia.com>

When processing command streams, make sure the host1x's stream ID is
programmed for the channel so that addresses are properly translated
through the SMMU.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/host1x/hw/channel_hw.c          | 12 ++++++++++++
 drivers/gpu/host1x/hw/host1x06_hardware.h   |  1 +
 drivers/gpu/host1x/hw/host1x07_hardware.h   |  1 +
 drivers/gpu/host1x/hw/hw_host1x06_channel.h | 11 +++++++++++
 drivers/gpu/host1x/hw/hw_host1x07_channel.h | 11 +++++++++++
 5 files changed, 36 insertions(+)
 create mode 100644 drivers/gpu/host1x/hw/hw_host1x06_channel.h
 create mode 100644 drivers/gpu/host1x/hw/hw_host1x07_channel.h

diff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw/channel_hw.c
index 95ea81172a83..ff137fe72d34 100644
--- a/drivers/gpu/host1x/hw/channel_hw.c
+++ b/drivers/gpu/host1x/hw/channel_hw.c
@@ -89,6 +89,16 @@ static inline void synchronize_syncpt_base(struct host1x_job *job)
 			 HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(value));
 }
 
+static void host1x_channel_set_streamid(struct host1x_channel *channel)
+{
+#if HOST1X_HW >= 6
+	struct iommu_fwspec *spec = dev_iommu_fwspec_get(channel->dev->parent);
+	u32 sid = spec->ids[0] & 0xffff;
+
+	host1x_ch_writel(channel, sid, HOST1X_CHANNEL_SMMU_STREAMID);
+#endif
+}
+
 static int channel_submit(struct host1x_job *job)
 {
 	struct host1x_channel *ch = job->channel;
@@ -120,6 +130,8 @@ static int channel_submit(struct host1x_job *job)
 		goto error;
 	}
 
+	host1x_channel_set_streamid(channel);
+
 	/* begin a CDMA submit */
 	err = host1x_cdma_begin(&ch->cdma, job);
 	if (err) {
diff --git a/drivers/gpu/host1x/hw/host1x06_hardware.h b/drivers/gpu/host1x/hw/host1x06_hardware.h
index 3039c92ea605..eab753b91f24 100644
--- a/drivers/gpu/host1x/hw/host1x06_hardware.h
+++ b/drivers/gpu/host1x/hw/host1x06_hardware.h
@@ -22,6 +22,7 @@
 #include <linux/types.h>
 #include <linux/bitops.h>
 
+#include "hw_host1x06_channel.h"
 #include "hw_host1x06_uclass.h"
 #include "hw_host1x06_vm.h"
 #include "hw_host1x06_hypervisor.h"
diff --git a/drivers/gpu/host1x/hw/host1x07_hardware.h b/drivers/gpu/host1x/hw/host1x07_hardware.h
index 1353e7ab71dd..a79f57dc87bb 100644
--- a/drivers/gpu/host1x/hw/host1x07_hardware.h
+++ b/drivers/gpu/host1x/hw/host1x07_hardware.h
@@ -22,6 +22,7 @@
 #include <linux/types.h>
 #include <linux/bitops.h>
 
+#include "hw_host1x07_channel.h"
 #include "hw_host1x07_uclass.h"
 #include "hw_host1x07_vm.h"
 #include "hw_host1x07_hypervisor.h"
diff --git a/drivers/gpu/host1x/hw/hw_host1x06_channel.h b/drivers/gpu/host1x/hw/hw_host1x06_channel.h
new file mode 100644
index 000000000000..18ae1c57bbea
--- /dev/null
+++ b/drivers/gpu/host1x/hw/hw_host1x06_channel.h
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 NVIDIA Corporation.
+ */
+
+#ifndef HOST1X_HW_HOST1X06_CHANNEL_H
+#define HOST1X_HW_HOST1X06_CHANNEL_H
+
+#define HOST1X_CHANNEL_SMMU_STREAMID 0x084
+
+#endif
diff --git a/drivers/gpu/host1x/hw/hw_host1x07_channel.h b/drivers/gpu/host1x/hw/hw_host1x07_channel.h
new file mode 100644
index 000000000000..96fa72bbd7ab
--- /dev/null
+++ b/drivers/gpu/host1x/hw/hw_host1x07_channel.h
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 NVIDIA Corporation.
+ */
+
+#ifndef HOST1X_HW_HOST1X07_CHANNEL_H
+#define HOST1X_HW_HOST1X07_CHANNEL_H
+
+#define HOST1X_CHANNEL_SMMU_STREAMID 0x084
+
+#endif
-- 
2.19.1

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  parent reply	other threads:[~2019-01-24 18:02 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-24 18:02 [PATCH v2 00/13] drm/tegra: Fix IOVA space on Tegra186 and later Thierry Reding
2019-01-24 18:02 ` [PATCH v2 01/13] gpu: host1x: Set up stream ID table Thierry Reding
2019-01-24 18:02 ` Thierry Reding [this message]
2019-01-24 18:02 ` [PATCH v2 03/13] gpu: host1x: Support 40-bit addressing Thierry Reding
2019-01-25  9:13   ` Mikko Perttunen
2019-01-25  9:20     ` Thierry Reding
2019-01-25  9:32       ` Mikko Perttunen
2019-01-25  9:34         ` Mikko Perttunen
2019-01-24 18:02 ` [PATCH v2 04/13] gpu: host1x: Use direct DMA with IOMMU API usage Thierry Reding
2019-01-28 14:30   ` Dmitry Osipenko
2019-01-24 18:02 ` [PATCH v2 05/13] gpu: host1x: Restrict IOVA space to DMA mask Thierry Reding
2019-01-24 18:02 ` [PATCH v2 06/13] gpu: host1x: Support 40-bit addressing on Tegra186 Thierry Reding
2019-01-24 18:02 ` [PATCH v2 07/13] drm/tegra: Store parent pointer in Tegra DRM clients Thierry Reding
2019-01-28 14:10   ` Dmitry Osipenko
2019-01-24 18:02 ` [PATCH v2 08/13] drm/tegra: vic: Load firmware on demand Thierry Reding
2019-01-28 14:12   ` Dmitry Osipenko
2019-01-24 18:02 ` [PATCH v2 09/13] drm/tegra: Setup shared IOMMU domain after initialization Thierry Reding
2019-01-24 18:02 ` [PATCH v2 10/13] drm/tegra: Restrict IOVA space to DMA mask Thierry Reding
2019-01-24 18:02 ` [PATCH v2 11/13] drm/tegra: vic: Do not clear driver data Thierry Reding
2019-01-24 18:02 ` [PATCH v2 12/13] drm/tegra: vic: Support stream ID register programming Thierry Reding
2019-01-24 18:02 ` [PATCH v2 13/13] arm64: tegra: Enable SMMU for VIC on Tegra186 Thierry Reding
2019-01-24 21:38 ` [PATCH v2 00/13] drm/tegra: Fix IOVA space on Tegra186 and later Dmitry Osipenko
2019-01-25  9:23   ` Thierry Reding
2019-01-25 13:14     ` Dmitry Osipenko
2019-01-24 21:53 ` Dmitry Osipenko
2019-01-25  8:57   ` Mikko Perttunen
2019-01-25 13:18     ` Dmitry Osipenko

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