From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A23F8C282C3 for ; Thu, 24 Jan 2019 19:42:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6E348218A2 for ; Thu, 24 Jan 2019 19:42:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1548358956; bh=N8tQMb6OhT3yaFMq6x514LN8pntOGSYMTF9gTTzCDus=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=rR96bS8jQXQ+rBOIP/uxsw5HGpeJ8qrFpQbdG3SifolNP+jUvCCFA4UUOtowGgElS z1i4MqqVBJ4IbaHPVC4846aJGGlF0qrObyiG7l24M+WsMO9BlLw5kqV2+CC8AaRTRQ +kzeja+QhZc5i2H68HRPO0Y9E8N7eYm0eews7y9k= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387807AbfAXTme (ORCPT ); Thu, 24 Jan 2019 14:42:34 -0500 Received: from mail.kernel.org ([198.145.29.99]:42982 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732659AbfAXTma (ORCPT ); Thu, 24 Jan 2019 14:42:30 -0500 Received: from localhost (5356596B.cm-6-7b.dynamic.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 983A1218D9; Thu, 24 Jan 2019 19:42:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1548358949; bh=N8tQMb6OhT3yaFMq6x514LN8pntOGSYMTF9gTTzCDus=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XEEjHDQBWoJCuLbqt292qgilOnxDjlY6vaCUniQmKK9I8+GxhLpHVBIIheavrPtN0 srW/vZiqDhVy8mv4aD1neTUmIc/0gW6kUueH27/WwmsSLzhfY3N09J2/QpoDmgvCtI 30wShq/pxlBnNlncLXox7QCcqwRlitjtc/9BI0rY= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Florian Fainelli , Will Deacon , Jiri Olsa , Alexander Shishkin , Namhyung Kim , Peter Zijlstra , Arnaldo Carvalho de Melo , Sasha Levin Subject: [PATCH 4.20 084/127] perf tests ARM: Disable breakpoint tests 32-bit Date: Thu, 24 Jan 2019 20:20:30 +0100 Message-Id: <20190124190215.674927507@linuxfoundation.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190124190211.984305387@linuxfoundation.org> References: <20190124190211.984305387@linuxfoundation.org> User-Agent: quilt/0.65 X-stable: review X-Patchwork-Hint: ignore MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 4.20-stable review patch. If anyone has any objections, please let me know. ------------------ [ Upstream commit 24f967337f6d6bce931425769c0f5ff5cf2d212e ] The breakpoint tests on the ARM 32-bit kernel are broken in several ways. The breakpoint length requested does not necessarily match whether the function address has the Thumb bit (bit 0) set or not, and this does matter to the ARM kernel hw_breakpoint infrastructure. See [1] for background. [1]: https://lkml.org/lkml/2018/11/15/205 As Will indicated, the overflow handling would require single-stepping which is not supported at the moment. Just disable those tests for the ARM 32-bit platforms and update the comment above to explain these limitations. Co-developed-by: Will Deacon Signed-off-by: Florian Fainelli Signed-off-by: Will Deacon Acked-by: Jiri Olsa Cc: Alexander Shishkin Cc: Namhyung Kim Cc: Peter Zijlstra Link: http://lkml.kernel.org/r/20181203191138.2419-1-f.fainelli@gmail.com Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Sasha Levin --- tools/perf/tests/bp_signal.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/tools/perf/tests/bp_signal.c b/tools/perf/tests/bp_signal.c index a467615c5a0e..910e25e64188 100644 --- a/tools/perf/tests/bp_signal.c +++ b/tools/perf/tests/bp_signal.c @@ -291,12 +291,20 @@ int test__bp_signal(struct test *test __maybe_unused, int subtest __maybe_unused bool test__bp_signal_is_supported(void) { -/* - * The powerpc so far does not have support to even create - * instruction breakpoint using the perf event interface. - * Once it's there we can release this. - */ -#if defined(__powerpc__) || defined(__s390x__) + /* + * PowerPC and S390 do not support creation of instruction + * breakpoints using the perf_event interface. + * + * ARM requires explicit rounding down of the instruction + * pointer in Thumb mode, and then requires the single-step + * to be handled explicitly in the overflow handler to avoid + * stepping into the SIGIO handler and getting stuck on the + * breakpointed instruction. + * + * Just disable the test for these architectures until these + * issues are resolved. + */ +#if defined(__powerpc__) || defined(__s390x__) || defined(__arm__) return false; #else return true; -- 2.19.1