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Thu, 31 Jan 2019 05:40:00 -0800 (PST) From: Bartosz Golaszewski To: Sekhar Nori , Kevin Hilman , Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH 16/35] ARM: davinci: aintc: move timer-specific irq_set_handler() out of irq.c Date: Thu, 31 Jan 2019 14:39:09 +0100 Message-Id: <20190131133928.17985-17-brgl@bgdev.pl> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190131133928.17985-1-brgl@bgdev.pl> References: <20190131133928.17985-1-brgl@bgdev.pl> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190131_054004_031490_3337C2D4 X-CRM114-Status: GOOD ( 14.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bartosz Golaszewski , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Bartosz Golaszewski I've been unable to figure out exactly why, but it seems that the IRQ_TINT1_TINT34 interrupt for timer 1 needs to be handled as a level irq, not edge like all others. This timer is used by the dsp on dm64* boards only. Let's move the handler setup out of the aintc driver where it's lived since the beginning and into the dm64* SoC-specific files where it belongs. Signed-off-by: Bartosz Golaszewski --- arch/arm/mach-davinci/dm644x.c | 4 ++++ arch/arm/mach-davinci/dm646x.c | 4 ++++ arch/arm/mach-davinci/irq.c | 1 - 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 24ad7a09aa15..beb97101c881 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -616,6 +617,9 @@ void __init dm644x_init_time(void) void __iomem *pll1, *psc; struct clk *clk; + /* Needed by the dsp. */ + irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq); + clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ); pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index ab02cc93813a..70505c92d5fb 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -599,6 +600,9 @@ void __init dm646x_init_time(unsigned long ref_clk_rate, void __iomem *pll1, *psc; struct clk *clk; + /* Needed by the dsp. */ + irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq); + clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate); clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate); diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c index d67f443a471d..2e114ad83adc 100644 --- a/arch/arm/mach-davinci/irq.c +++ b/arch/arm/mach-davinci/irq.c @@ -142,6 +142,5 @@ void __init davinci_aintc_init(const struct davinci_aintc_config *config) davinci_aintc_setup_gc(davinci_aintc_base + reg_off, irq_base + irq_off, 32); - irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq); set_handle_irq(davinci_aintc_handle_irq); } -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=DKIMWL_WL_MED,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02DA7C282DA for ; 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Thu, 31 Jan 2019 05:40:00 -0800 (PST) Received: from debian-brgl.home ([2a01:cb1d:af:5b00:6d6c:8493:1ab5:dad7]) by smtp.gmail.com with ESMTPSA id h10sm5479768wmf.44.2019.01.31.05.39.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Jan 2019 05:40:00 -0800 (PST) From: Bartosz Golaszewski To: Sekhar Nori , Kevin Hilman , Thomas Gleixner , Jason Cooper , Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH 16/35] ARM: davinci: aintc: move timer-specific irq_set_handler() out of irq.c Date: Thu, 31 Jan 2019 14:39:09 +0100 Message-Id: <20190131133928.17985-17-brgl@bgdev.pl> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190131133928.17985-1-brgl@bgdev.pl> References: <20190131133928.17985-1-brgl@bgdev.pl> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Bartosz Golaszewski I've been unable to figure out exactly why, but it seems that the IRQ_TINT1_TINT34 interrupt for timer 1 needs to be handled as a level irq, not edge like all others. This timer is used by the dsp on dm64* boards only. Let's move the handler setup out of the aintc driver where it's lived since the beginning and into the dm64* SoC-specific files where it belongs. Signed-off-by: Bartosz Golaszewski --- arch/arm/mach-davinci/dm644x.c | 4 ++++ arch/arm/mach-davinci/dm646x.c | 4 ++++ arch/arm/mach-davinci/irq.c | 1 - 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 24ad7a09aa15..beb97101c881 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -616,6 +617,9 @@ void __init dm644x_init_time(void) void __iomem *pll1, *psc; struct clk *clk; + /* Needed by the dsp. */ + irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq); + clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ); pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index ab02cc93813a..70505c92d5fb 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -599,6 +600,9 @@ void __init dm646x_init_time(unsigned long ref_clk_rate, void __iomem *pll1, *psc; struct clk *clk; + /* Needed by the dsp. */ + irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq); + clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate); clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate); diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c index d67f443a471d..2e114ad83adc 100644 --- a/arch/arm/mach-davinci/irq.c +++ b/arch/arm/mach-davinci/irq.c @@ -142,6 +142,5 @@ void __init davinci_aintc_init(const struct davinci_aintc_config *config) davinci_aintc_setup_gc(davinci_aintc_base + reg_off, irq_base + irq_off, 32); - irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq); set_handle_irq(davinci_aintc_handle_irq); } -- 2.20.1