[MODERATED] Re: [PATCH v1 9/9] PERFv1 3

[Andi Kleen <ak@linux.intel.com>]

On Tue, Feb 05, 2019 at 04:28:04PM +0100, speck for Peter Zijlstra wrote:
> On Mon, Feb 04, 2019 at 05:14:10PM -0800, speck for Andi Kleen wrote:
> > From: Andi Kleen <ak@linux.intel.com>
> > Subject:  kvm: vmx: Support TSX_FORCE_ABORT in KVM guests
> > 
> > Recent microcode for Skylake added a new CPUID bit and MSR to control
> > TSX aborting and enabling PMU counter 3. This patch adds support
> > for controlling counter 3 from KVM guests.
> > 
> > The implementation is similar to how SPEC_CTRL is implemented. Initially
> > the MSR is just intercepted, to avoid any impact on the entry/exit.
> > When the guest uses the MSR the first time add the MSR to the
> > entry/exit list to context switch it against the host.
> > 
> 
> What this does not explain is how the guest can ever possibly use this
> correctly, since it doesn't have access to PMC3.

Yes you're right. In the current form it is only useful for
people who really want to disable TSX and don't care about the PMU.

But we should really care about the PMU.
I guess we can force the flag on the KVM PMU events instead.

Then the host perf will do the right thing.

It won't allow a guest to disable TSX for some other reason, 
but i guess that's ok.

-Andi