From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (146.0.238.70:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 05 Feb 2019 18:20:22 -0000 Received: from mail.kernel.org ([198.145.29.99]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1gr5KW-0004p5-Dc for speck@linutronix.de; Tue, 05 Feb 2019 19:20:20 +0100 Date: Tue, 5 Feb 2019 19:20:00 +0100 From: Greg KH Subject: [MODERATED] Re: [PATCH v1 0/9] PERFv1 0 Message-ID: <20190205182000.GA20380@kroah.com> References: <20190205140329.GA16924@kroah.com> <20190205163648.GF31598@tassilo.jf.intel.com> MIME-Version: 1.0 In-Reply-To: <20190205163648.GF31598@tassilo.jf.intel.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Tue, Feb 05, 2019 at 08:36:48AM -0800, speck for Andi Kleen wrote: > On Tue, Feb 05, 2019 at 03:03:29PM +0100, speck for Greg KH wrote: > > On Mon, Feb 04, 2019 at 05:14:01PM -0800, speck for Andi Kleen wrote: > > > v1: Initial post > > > > > > Andi Kleen (9): > > > x86/pmu/intel: Export number of counters in caps > > > x86/pmu/intel: Add flags argument to x86_pmu::disable > > > x86/pmu/intel: Support excluding GP counters in scheduler > > > x86/pmu/intel: Handle TSX with counter 3 on Skylake > > > x86/pmu/intel: Add perf event attribute to enable counter 3 > > > x86/pmu/intel: Add global option for enable all counters > > > perf stat: Make all existing groups weak > > > perf stat: Don't count EL for --transaction with three counters > > > kvm: vmx: Support TSX_FORCE_ABORT in KVM guests > > > > Meta-comment, can you fix up and use the updated script to post these? > > The [XX/NN] and "N" numbers do not match up at all and it's hard to > > figure out which to trust. > > I'm just using Thomas' script. Let me post a mbox. He posted a fix for the script to address this issue, so if you could use that next time, that would make reviewing a lot easier. thanks, greg k-h