From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter Zijlstra Subject: Re: [PATCH-tip 15/22] locking/rwsem: Merge owner into count on x86-64 Date: Thu, 7 Feb 2019 20:45:42 +0100 Message-ID: <20190207194542.GG32511@hirez.programming.kicks-ass.net> References: <1549566446-27967-1-git-send-email-longman@redhat.com> <1549566446-27967-16-git-send-email-longman@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qJ4R4vKR5Gh3TUQ3aR+hUsBRzfAA3J2RckeljmJSAzU=; b=kz++8QFGUz+34b LQLDKTGHCj1zjdmo5ad3IsZ1VnNeLXoiol0j4xUrEHL1zPS0a0WlBEmpX7QNLebFlM4zyntiwJQRJ fsmNTjJGkfLracSEyFf5wMWh7EaKv4vKgRKU5HXGEWIQJefQwkq9vpVj1V5hBi/D+Nhr/HfSmHSBo hclevqIlWDC72LTt3ac/nWXrWJWf/mgkh4kDptvK++SwHXC7q7FVAGiU8YIVMWaYAZApekr2I5iv4 pGysHU+EdUCZw6F3a/AOibRnRruX02uSAOK9At65OurqOaKw+d8ezC80oPOEBJUCpSE1Ip8pwXv53 zMsSyR9KwSRtNvBUThjA==; DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=merlin.20170209; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=d2Auinqj+iinWuACUh1zWQLvdx+uvY34M1d8kVvscRo=; b=GD6MNJTH7ahxODIJwjMRtXdnR RGD+hw9J+ZDL8sz/xbv/d7Zqgil1ESzAyfO7J6vTAR0eOBQbKA+2n1dr0BkrZrWBaHsHiinLNErB3 g+h3oZHOrxMVq84OJ9xWE4MvvJNsJ7gMZziSCkHMHlorLYek/Ay+0h+X4Ff02okQAYSM9Q9kbsEYG sP6vzRH/Aw3OMOnEjV905Mx2248RvsaFgDw5pfYmQN1OH4MoKxYYnGwKbb1rQt3d/GT/GYTWx5Omh KzbHIoABiKb148eXjHvwxsrvCmrg26erty1ERFcwZ5kSKWjGzDj0O5Sh8u0FqWgxN6v7ekPCAzKqa wmJhspFPg==; Content-Disposition: inline In-Reply-To: <1549566446-27967-16-git-send-email-longman@redhat.com> List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Waiman Long Cc: linux-arch@vger.kernel.org, linux-xtensa@linux-xtensa.org, Davidlohr Bueso , linux-ia64@vger.kernel.org, Tim Chen , Arnd Bergmann , linux-sh@vger.kernel.org, linux-hexagon@vger.kernel.org, x86@kernel.org, Will Deacon , linux-kernel@vger.kernel.org, Linus Torvalds , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, Thomas Gleixner , linuxppc-dev@lists.ozlabs.org, Andrew Morton , linux-arm-kernel@lists.infradead.org On Thu, Feb 07, 2019 at 02:07:19PM -0500, Waiman Long wrote: > On 32-bit architectures, there aren't enough bits to hold both. > 64-bit architectures, however, can have enough bits to do that. For > x86-64, the physical address can use up to 52 bits. That is 4PB of > memory. That leaves 12 bits available for other use. The task structure > pointer is also aligned to the L1 cache size. That means another 6 bits > (64 bytes cacheline) will be available. Reserving 2 bits for status > flags, we will have 16 bits for the reader count. That can supports > up to (64k-1) readers. *groan*... So take qrwlock's idea for a queue, then make the count value (similar to the new mutex); that is have a bit0 be a r/w bit, when w bits 6-N are owner, when r they are reader-count. bit1 can be a pending bit, bit2 a handoff bit etc.. That should fit and work on 32bit and 64bit without issue. I have a half-arsed rwsem-atomic.c somewhere that does just that. I just never got around to doing all the optimistic spin and steal crap that makes our current rwsem fly. And that nicely gets rid of that mind bending BIAS crud. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from merlin.infradead.org ([205.233.59.134]:45574 "EHLO merlin.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726401AbfBGTqP (ORCPT ); Thu, 7 Feb 2019 14:46:15 -0500 Date: Thu, 7 Feb 2019 20:45:42 +0100 From: Peter Zijlstra Subject: Re: [PATCH-tip 15/22] locking/rwsem: Merge owner into count on x86-64 Message-ID: <20190207194542.GG32511@hirez.programming.kicks-ass.net> References: <1549566446-27967-1-git-send-email-longman@redhat.com> <1549566446-27967-16-git-send-email-longman@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1549566446-27967-16-git-send-email-longman@redhat.com> Sender: linux-arch-owner@vger.kernel.org List-ID: To: Waiman Long Cc: Ingo Molnar , Will Deacon , Thomas Gleixner , linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hexagon@vger.kernel.org, linux-ia64@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-xtensa@linux-xtensa.org, linux-arch@vger.kernel.org, x86@kernel.org, Arnd Bergmann , Borislav Petkov , "H. Peter Anvin" , Davidlohr Bueso , Linus Torvalds , Andrew Morton , Tim Chen Message-ID: <20190207194542.k8PhQ8S7M0fKnX1Mp7h8pOUOzJrcf7IwLa0AmjHCROw@z> On Thu, Feb 07, 2019 at 02:07:19PM -0500, Waiman Long wrote: > On 32-bit architectures, there aren't enough bits to hold both. > 64-bit architectures, however, can have enough bits to do that. For > x86-64, the physical address can use up to 52 bits. That is 4PB of > memory. That leaves 12 bits available for other use. The task structure > pointer is also aligned to the L1 cache size. That means another 6 bits > (64 bytes cacheline) will be available. Reserving 2 bits for status > flags, we will have 16 bits for the reader count. That can supports > up to (64k-1) readers. *groan*... So take qrwlock's idea for a queue, then make the count value (similar to the new mutex); that is have a bit0 be a r/w bit, when w bits 6-N are owner, when r they are reader-count. bit1 can be a pending bit, bit2 a handoff bit etc.. That should fit and work on 32bit and 64bit without issue. I have a half-arsed rwsem-atomic.c somewhere that does just that. I just never got around to doing all the optimistic spin and steal crap that makes our current rwsem fly. And that nicely gets rid of that mind bending BIAS crud. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter Zijlstra Date: Thu, 07 Feb 2019 19:45:42 +0000 Subject: Re: [PATCH-tip 15/22] locking/rwsem: Merge owner into count on x86-64 Message-Id: <20190207194542.GG32511@hirez.programming.kicks-ass.net> List-Id: References: <1549566446-27967-1-git-send-email-longman@redhat.com> <1549566446-27967-16-git-send-email-longman@redhat.com> In-Reply-To: <1549566446-27967-16-git-send-email-longman@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Waiman Long Cc: linux-arch@vger.kernel.org, linux-xtensa@linux-xtensa.org, Davidlohr Bueso , linux-ia64@vger.kernel.org, Tim Chen , Arnd Bergmann , linux-sh@vger.kernel.org, linux-hexagon@vger.kernel.org, x86@kernel.org, Will Deacon , linux-kernel@vger.kernel.org, Linus Torvalds , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, Thomas Gleixner , linuxppc-dev@lists.ozlabs.org, Andrew Morton , linux-arm-kernel@lists.infradead.org On Thu, Feb 07, 2019 at 02:07:19PM -0500, Waiman Long wrote: > On 32-bit architectures, there aren't enough bits to hold both. > 64-bit architectures, however, can have enough bits to do that. For > x86-64, the physical address can use up to 52 bits. That is 4PB of > memory. That leaves 12 bits available for other use. The task structure > pointer is also aligned to the L1 cache size. That means another 6 bits > (64 bytes cacheline) will be available. Reserving 2 bits for status > flags, we will have 16 bits for the reader count. That can supports > up to (64k-1) readers. *groan*... So take qrwlock's idea for a queue, then make the count value (similar to the new mutex); that is have a bit0 be a r/w bit, when w bits 6-N are owner, when r they are reader-count. bit1 can be a pending bit, bit2 a handoff bit etc.. That should fit and work on 32bit and 64bit without issue. I have a half-arsed rwsem-atomic.c somewhere that does just that. I just never got around to doing all the optimistic spin and steal crap that makes our current rwsem fly. And that nicely gets rid of that mind bending BIAS crud. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33B19C282C2 for ; Thu, 7 Feb 2019 19:45:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EF5E721872 for ; Thu, 7 Feb 2019 19:45:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="kz++8QFG"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="GD6MNJTH" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EF5E721872 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=infradead.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qJ4R4vKR5Gh3TUQ3aR+hUsBRzfAA3J2RckeljmJSAzU=; b=kz++8QFGUz+34b LQLDKTGHCj1zjdmo5ad3IsZ1VnNeLXoiol0j4xUrEHL1zPS0a0WlBEmpX7QNLebFlM4zyntiwJQRJ fsmNTjJGkfLracSEyFf5wMWh7EaKv4vKgRKU5HXGEWIQJefQwkq9vpVj1V5hBi/D+Nhr/HfSmHSBo hclevqIlWDC72LTt3ac/nWXrWJWf/mgkh4kDptvK++SwHXC7q7FVAGiU8YIVMWaYAZApekr2I5iv4 pGysHU+EdUCZw6F3a/AOibRnRruX02uSAOK9At65OurqOaKw+d8ezC80oPOEBJUCpSE1Ip8pwXv53 zMsSyR9KwSRtNvBUThjA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1grpcR-00039k-VM; Thu, 07 Feb 2019 19:45:55 +0000 Received: from merlin.infradead.org ([2001:8b0:10b:1231::1]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1grpcP-00039e-U0 for linux-arm-kernel@bombadil.infradead.org; Thu, 07 Feb 2019 19:45:53 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=merlin.20170209; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=d2Auinqj+iinWuACUh1zWQLvdx+uvY34M1d8kVvscRo=; b=GD6MNJTH7ahxODIJwjMRtXdnR RGD+hw9J+ZDL8sz/xbv/d7Zqgil1ESzAyfO7J6vTAR0eOBQbKA+2n1dr0BkrZrWBaHsHiinLNErB3 g+h3oZHOrxMVq84OJ9xWE4MvvJNsJ7gMZziSCkHMHlorLYek/Ay+0h+X4Ff02okQAYSM9Q9kbsEYG sP6vzRH/Aw3OMOnEjV905Mx2248RvsaFgDw5pfYmQN1OH4MoKxYYnGwKbb1rQt3d/GT/GYTWx5Omh KzbHIoABiKb148eXjHvwxsrvCmrg26erty1ERFcwZ5kSKWjGzDj0O5Sh8u0FqWgxN6v7ekPCAzKqa wmJhspFPg==; Received: from j217100.upc-j.chello.nl ([24.132.217.100] helo=hirez.programming.kicks-ass.net) by merlin.infradead.org with esmtpsa (Exim 4.90_1 #2 (Red Hat Linux)) id 1grpcH-00070v-BQ; Thu, 07 Feb 2019 19:45:45 +0000 Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 01FBD2029E062; Thu, 7 Feb 2019 20:45:42 +0100 (CET) Date: Thu, 7 Feb 2019 20:45:42 +0100 From: Peter Zijlstra To: Waiman Long Subject: Re: [PATCH-tip 15/22] locking/rwsem: Merge owner into count on x86-64 Message-ID: <20190207194542.GG32511@hirez.programming.kicks-ass.net> References: <1549566446-27967-1-git-send-email-longman@redhat.com> <1549566446-27967-16-git-send-email-longman@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1549566446-27967-16-git-send-email-longman@redhat.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, linux-xtensa@linux-xtensa.org, Davidlohr Bueso , linux-ia64@vger.kernel.org, Tim Chen , Arnd Bergmann , linux-sh@vger.kernel.org, linux-hexagon@vger.kernel.org, x86@kernel.org, Will Deacon , linux-kernel@vger.kernel.org, Linus Torvalds , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, Thomas Gleixner , linuxppc-dev@lists.ozlabs.org, Andrew Morton , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Feb 07, 2019 at 02:07:19PM -0500, Waiman Long wrote: > On 32-bit architectures, there aren't enough bits to hold both. > 64-bit architectures, however, can have enough bits to do that. For > x86-64, the physical address can use up to 52 bits. That is 4PB of > memory. That leaves 12 bits available for other use. The task structure > pointer is also aligned to the L1 cache size. That means another 6 bits > (64 bytes cacheline) will be available. Reserving 2 bits for status > flags, we will have 16 bits for the reader count. That can supports > up to (64k-1) readers. *groan*... So take qrwlock's idea for a queue, then make the count value (similar to the new mutex); that is have a bit0 be a r/w bit, when w bits 6-N are owner, when r they are reader-count. bit1 can be a pending bit, bit2 a handoff bit etc.. That should fit and work on 32bit and 64bit without issue. I have a half-arsed rwsem-atomic.c somewhere that does just that. I just never got around to doing all the optimistic spin and steal crap that makes our current rwsem fly. And that nicely gets rid of that mind bending BIAS crud. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel