From: Bjorn Helgaas <helgaas@kernel.org>
To: Ingo Molnar <mingo@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>,
x86@kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH v2] PCI: Fixup the RTIT_BAR of Intel TH on Denverton
Date: Mon, 11 Feb 2019 08:42:05 -0600 [thread overview]
Message-ID: <20190211144205.GB151039@google.com> (raw)
In-Reply-To: <20190211074141.GA49295@gmail.com>
On Mon, Feb 11, 2019 at 08:41:41AM +0100, Ingo Molnar wrote:
>
> * Alexander Shishkin <alexander.shishkin@linux.intel.com> wrote:
>
> > On Denverton's integration of the Intel(R) Trace Hub (for a reference
> > and overview see Documentation/trace/intel_th.txt) the reported size of
> > one of its resources (RTIT_BAR) doesn't match its actual size, which
> > leads to overlaps with other devices' resources.
>
> Note that in the latest kernels it's Documentation/trace/intel_th.rst,
> not .txt.
I fixed this, thanks, Ingo!
next prev parent reply other threads:[~2019-02-11 15:46 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-07 13:30 [PATCH v2] PCI: Fixup the RTIT_BAR of Intel TH on Denverton Alexander Shishkin
2019-02-07 15:02 ` Bjorn Helgaas
2019-02-11 7:41 ` Ingo Molnar
2019-02-11 14:42 ` Bjorn Helgaas [this message]
[not found] ` <20190211172611.505A2222A2@mail.kernel.org>
2019-02-11 20:20 ` Bjorn Helgaas
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