From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9ABDFC169C4 for ; Tue, 12 Feb 2019 01:21:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 68245214DA for ; Tue, 12 Feb 2019 01:21:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="EBZV7ixm" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726699AbfBLBVc (ORCPT ); Mon, 11 Feb 2019 20:21:32 -0500 Received: from vps0.lunn.ch ([185.16.172.187]:47641 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726079AbfBLBVb (ORCPT ); Mon, 11 Feb 2019 20:21:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Transfer-Encoding:Content-Type:MIME-Version :References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=4ln5s0BFiAs8K4bm4s87bHXxfwOdpupdm0AfDdopDns=; b=EBZV7ixmaPvNL6Mdpsk6Woz8CF V3Dxp37pnmd5tipQDG+fIU7FGLgdv+gOXbT0L+Z0jfqC1DZOk+8lbNYyEZrqk0B94lNA3rUnWNetX bAMw+5GEs2WcYDzfGcsJ+BPXUqsWlri7ne33nGJWw+fDU7P5Lwi9qBlG/2UkwO3CnURk=; Received: from andrew by vps0.lunn.ch with local (Exim 4.89) (envelope-from ) id 1gtMlK-0005za-6R; Tue, 12 Feb 2019 02:21:26 +0100 Date: Tue, 12 Feb 2019 02:21:26 +0100 From: Andrew Lunn To: John David Anglin Cc: Russell King , Vivien Didelot , Florian Fainelli , netdev@vger.kernel.org Subject: Re: [PATCH net] dsa: mv88e6xxx: Ensure all pending interrupts are handled prior to exit Message-ID: <20190212012126.GC19023@lunn.ch> References: <20190130172818.GJ21904@lunn.ch> <2ea9fd81-f92d-9505-dd0b-bdd0f67d8ce7@bell.net> <20190130223846.GB30115@lunn.ch> <9415d82e-965b-7777-0ad0-f23d6c9f177e@bell.net> <53b49df8-53ed-704f-9197-230b18d83090@bell.net> <824d011b-3692-69c3-5e2c-58e950a80abf@bell.net> <6a1ebc61-3505-beb8-21cb-ea42ad9fe67e@bell.net> <20190211233327.GB8591@lunn.ch> <2b6bbb4c-1346-461b-ff7a-cb96b4142f7a@bell.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <2b6bbb4c-1346-461b-ff7a-cb96b4142f7a@bell.net> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org > Yes, it is true the PHY and SERDES enables in Global 2 should be > cleared before the interrupt handler is installed for device > interrupts.  That's what is done for the interrupts enables in > Global 1.  I'm not seeing that these enables are initialized. > > Which switch? 6390X. > The device interrupts are not be cleared properly on that board. I added in code to mask all interrupts. It did not help. I need to go deeper and see if it is a PHY problem. > I suspect the same would happen if level interrupts were used. I've not seen it loop. Which is why i want to understand it fully. Andrew