[U-Boot] [RFC PATCH 3/3] sunxi: Fix A33 memory initialization

[Michael Trimarchi <michael@amarulasolutions.com>]

Set two rank timing and exit self-refresh timing seems not done
properly. We know use the same write that we are using
on H5 silicon.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
---
 arch/arm/mach-sunxi/dram_sun8i_a33.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c b/arch/arm/mach-sunxi/dram_sun8i_a33.c
index d73a93a132..355fe30aba 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_a33.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c
@@ -146,7 +146,7 @@ static void auto_set_timing_para(struct dram_para *para)
 	writel(reg_val, &mctl_ctl->dramtmg5);
 	/* Set two rank timing and exit self-refresh timing */
 	clrsetbits_le32(&mctl_ctl->dramtmg8, (0xff << 8) | (0xff << 0),
-			0x33 << 8 | (0x8 << 0));
+			0x33 << 8 | (0x10 << 0));
 	/* Set phy interface time */
 	reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)
 			| (wr_latency << 0);
-- 
2.17.1