From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS, URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1BCDC43381 for ; Thu, 14 Feb 2019 02:07:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 997C9222A4 for ; Thu, 14 Feb 2019 02:07:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="WNFDRr64" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390133AbfBNCHb (ORCPT ); Wed, 13 Feb 2019 21:07:31 -0500 Received: from vps0.lunn.ch ([185.16.172.187]:51044 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726148AbfBNCHb (ORCPT ); Wed, 13 Feb 2019 21:07:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Type:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=7gT7aqCXPb3/lnhr2XXo1viPtZKulwxcGijZ3NYOAPc=; b=WNFDRr64tXpgrJXZiBBYb89PGv 6jQaCYalY5SLuLi4Wc/7fvRAQaZckX3gljrccuTCZPw7NlV+tk24WFu9ZKCh1fU7kRzBnRmSvXocN DDilNpx/At5cD/J93VXeqwLj0KxNzst43LYpBb/qICLxFm8D5fSO8rI8TGxwFna5tDm8=; Received: from andrew by vps0.lunn.ch with local (Exim 4.89) (envelope-from ) id 1gu6Qt-0004Mo-Vk; Thu, 14 Feb 2019 03:07:23 +0100 Date: Thu, 14 Feb 2019 03:07:23 +0100 From: Andrew Lunn To: John David Anglin Cc: Russell King , Vivien Didelot , Florian Fainelli , netdev@vger.kernel.org Subject: Re: [PATCH net] dsa: mv88e6xxx: Ensure all pending interrupts are handled prior to exit Message-ID: <20190214020723.GE24589@lunn.ch> References: <20190123002240.GF3634@lunn.ch> <20190130172818.GJ21904@lunn.ch> <2ea9fd81-f92d-9505-dd0b-bdd0f67d8ce7@bell.net> <20190130223846.GB30115@lunn.ch> <9415d82e-965b-7777-0ad0-f23d6c9f177e@bell.net> <53b49df8-53ed-704f-9197-230b18d83090@bell.net> <824d011b-3692-69c3-5e2c-58e950a80abf@bell.net> <6a1ebc61-3505-beb8-21cb-ea42ad9fe67e@bell.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <6a1ebc61-3505-beb8-21cb-ea42ad9fe67e@bell.net> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Mon, Feb 11, 2019 at 01:40:21PM -0500, John David Anglin wrote: > The GPIO interrupt controller on the espressobin board only supports edge interrupts. > If one enables the use of hardware interrupts in the device tree for the 88E6341, it is > possible to miss an edge. When this happens, the INTn pin on the Marvell switch is > stuck low and no further interrupts occur. > > I found after adding debug statements to mv88e6xxx_g1_irq_thread_work() that there is > a race in handling device interrupts (e.g. PHY link interrupts). Some interrupts are > directly cleared by reading the Global 1 status register. However, the device interrupt > flag, for example, is not cleared until all the unmasked SERDES and PHY ports are serviced. > This is done by reading the relevant SERDES and PHY status register. > > The code only services interrupts whose status bit is set at the time of reading its status > register. If an interrupt event occurs after its status is read and before all interrupts > are serviced, then this event will not be serviced and the INTn output pin will remain low. > > This is not a problem with polling or level interrupts since the handler will be called > again to process the event. However, it's a big problem when using level interrupts. > > The fix presented here is to add a loop around the code servicing switch interrupts. If > any pending interrupts remain after the current set has been handled, we loop and process > the new set. If there are no pending interrupts after servicing, we are sure that INTn has > gone high and we will get an edge when a new event occurs. > > Tested on espressobin board. > > Signed-off-by: John David Anglin Fixes: dc30c35be720 ("net: dsa: mv88e6xxx: Implement interrupt support.") Tested-by: Andrew Lunn David, please ensure that Heiner's patch: net: phy: fix interrupt handling in non-started states is applied first. Otherwise we can get into an interrupt storm. Andrew