From mboxrd@z Thu Jan  1 00:00:00 1970
From: Andi Kleen <ak@linux.intel.com>
Subject: Re: [PATCH v5 12/12] KVM/VMX/vPMU: support to report
 GLOBAL_STATUS_LBRS_FROZEN
Date: Thu, 14 Feb 2019 08:31:47 -0800
Message-ID: <20190214163147.GL16922@tassilo.jf.intel.com>
References: <1550135174-5423-1-git-send-email-wei.w.wang@intel.com>
 <1550135174-5423-13-git-send-email-wei.w.wang@intel.com>
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Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
        pbonzini@redhat.com, peterz@infradead.org, kan.liang@intel.com,
        mingo@redhat.com, rkrcmar@redhat.com, like.xu@intel.com,
        jannh@google.com, arei.gonglei@huawei.com, jmattson@google.com
To: Wei Wang <wei.w.wang@intel.com>
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> +static void intel_pmu_get_global_status(struct kvm_pmu *pmu,
> +					struct msr_data *msr_info)
> +{
> +	u64 guest_debugctl, freeze_lbr_bits = DEBUGCTLMSR_FREEZE_LBRS_ON_PMI |
> +					      DEBUGCTLMSR_LBR;
> +
> +	if (!pmu->global_status) {
> +		msr_info->data = 0;
> +		return;
> +	}
> +
> +	msr_info->data = pmu->global_status;
> +	if (pmu->version >= 4) {
> +		guest_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
> +		if ((guest_debugctl & freeze_lbr_bits) == freeze_lbr_bits)

It should only check for the freeze bit, the freeze bit can be set
even when LBRs are disabled.

Also you seem to set the bit unconditionally?
That doesn't seem right. It should only be set after an overflow.

So the PMI injection needs to set it.

-Andi