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Date:   Tue, 19 Feb 2019 16:40:52 +0100
From:   Andrew Lunn <andrew@lunn.ch>
To:     Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Cc:     Florian Fainelli <f.fainelli@gmail.com>,
        Heiner Kallweit <hkallweit1@gmail.com>, netdev@vger.kernel.org,
        Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
        =?iso-8859-1?Q?Myl=E8ne?= Josserand 
        <mylene.josserand@bootlin.com>
Subject: Re: Handling an Extra Signal at PHY Reset
Message-ID: <20190219154052.GC1981@lunn.ch>
References: <e647050a0fbadb8445cf6a7a5a2ccfbfd0865592.camel@bootlin.com>
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> I think the reason why we need to deal with the CONFIG pin is more
> about setting the correct I/O voltage than the PHY address (it just
> happens that the CONFIG pin configures both at once).

Hi Paul

I don't have the datasheet...

What I/O voltages are we talking about? Is the device addressable over
the MDIO bus without this configuration? Can the voltages be
configured via register writes during probe? I assume not, or you
would be doing that...

      Andrew