From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (146.0.238.70:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 19 Feb 2019 16:07:59 -0000 Received: from mga06.intel.com ([134.134.136.31]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1gw7w5-00016T-Na for speck@linutronix.de; Tue, 19 Feb 2019 17:07:58 +0100 Date: Tue, 19 Feb 2019 08:07:54 -0800 From: Andi Kleen Subject: [MODERATED] Re: [patch 4/8] MDS basics 4 Message-ID: <20190219160754.GS16922@tassilo.jf.intel.com> References: <20190219124406.449727187@linutronix.de> <20190219125346.141295571@linutronix.de> MIME-Version: 1.0 In-Reply-To: <20190219125346.141295571@linutronix.de> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Tue, Feb 19, 2019 at 01:44:10PM +0100, speck for Thomas Gleixner wrote: > Subject: [patch 4/8] x86/speculation/mds: Conditionaly clear CPU buffers on idle entry > From: Thomas Gleixner > > Add a static key which controls the invocation of the CPU buffer clear > mechanism on idle entry. This is independent of other MDS mitigations > because the idle entry invocation to mitigate the potential leakage due to > store buffer repartitioning is only necessary on SMT systems. > > Add the actual invocations to the different halt/mwait variants which > covers all usage sites. mwaitx is not patched as it's not available on > Intel CPUs. This doesn't handle ACPI IO port idling correctly. -Andi