From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (146.0.238.70:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 19 Feb 2019 16:08:33 -0000 Received: from mga03.intel.com ([134.134.136.65]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1gw7wd-0001DP-Sp for speck@linutronix.de; Tue, 19 Feb 2019 17:08:32 +0100 Date: Tue, 19 Feb 2019 08:08:30 -0800 From: Andi Kleen Subject: [MODERATED] Re: [patch 4/8] MDS basics 4 Message-ID: <20190219160829.GT16922@tassilo.jf.intel.com> References: <20190219124406.449727187@linutronix.de> <20190219125346.141295571@linutronix.de> <7f92c34c-a3c4-1df2-c026-c7309c6ff3f2@citrix.com> MIME-Version: 1.0 In-Reply-To: <7f92c34c-a3c4-1df2-c026-c7309c6ff3f2@citrix.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Tue, Feb 19, 2019 at 01:54:55PM +0000, speck for Andrew Cooper wrote: > On 19/02/2019 12:44, speck for Thomas Gleixner wrote: > > Subject: [patch 4/8] x86/speculation/mds: Conditionaly clear CPU buffers on idle entry > > From: Thomas Gleixner > > > > Add a static key which controls the invocation of the CPU buffer clear > > mechanism on idle entry. This is independent of other MDS mitigations > > because the idle entry invocation to mitigate the potential leakage due to > > store buffer repartitioning is only necessary on SMT systems. > > > > Add the actual invocations to the different halt/mwait variants which > > covers all usage sites. mwaitx is not patched as it's not available on > > Intel CPUs. > > > > Signed-off-by: Thomas Gleixner > > Unfortunately, clearing is needed on the exit from idle as well as the > entry. Not with the full flush. There it would always clear on next kernel exit. -Andi