From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dmitry Osipenko Subject: [PATCH v5 5/8] ARM: tegra: Don't apply CPU erratas in insecure mode Date: Fri, 22 Feb 2019 20:59:23 +0300 Message-ID: <20190222175926.23366-6-digetx@gmail.com> References: <20190222175926.23366-1-digetx@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <20190222175926.23366-1-digetx@gmail.com> Sender: linux-kernel-owner@vger.kernel.org To: Russell King , Thierry Reding , Jonathan Hunter , Robert Yang , =?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?= Cc: linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: linux-tegra@vger.kernel.org CPU isn't allowed to touch secure registers while running under secure monitor. Hence skip applying of CPU erratas in the reset handler if Trusted Foundations firmware presents. Partially based on work done by Michał Mirosław [1]. [1] https://www.spinics.net/lists/arm-kernel/msg594768.html Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/reset-handler.S | 23 ++++++++++++----------- arch/arm/mach-tegra/reset.c | 3 +++ arch/arm/mach-tegra/reset.h | 9 +++++++-- arch/arm/mach-tegra/sleep-tegra20.S | 4 ++++ 4 files changed, 26 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 805f306fa6f7..6bea95d165fa 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -29,8 +29,6 @@ #define PMC_SCRATCH41 0x140 -#define RESET_DATA(x) ((TEGRA_RESET_##x)*4) - #ifdef CONFIG_PM_SLEEP /* * tegra_resume @@ -121,6 +119,12 @@ ENTRY(__tegra_cpu_reset_handler) cpsid aif, 0x13 @ SVC mode, interrupts disabled tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 + + adr r12, __tegra_cpu_reset_handler_data + ldr r5, [r12, #RESET_DATA(TF_PRESENT)] + cmp r5, #0 + bne after_errata + #ifdef CONFIG_ARCH_TEGRA_2x_SOC t20_check: cmp r6, #TEGRA20 @@ -155,7 +159,6 @@ after_errata: and r10, r10, #0x3 @ R10 = CPU number mov r11, #1 mov r11, r11, lsl r10 @ R11 = CPU mask - adr r12, __tegra_cpu_reset_handler_data #ifdef CONFIG_SMP /* Does the OS know about this CPU? */ @@ -169,10 +172,9 @@ after_errata: cmp r6, #TEGRA20 bne 1f /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */ - mov32 r5, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET mov r0, #CPU_NOT_RESETTABLE cmp r10, #0 - strneb r0, [r5, #__tegra20_cpu1_resettable_status_offset] + strneb r0, [r12, #RESET_DATA(RESETTABLE_STATUS)] 1: #endif @@ -277,14 +279,13 @@ ENDPROC(__tegra_cpu_reset_handler) .align L1_CACHE_SHIFT .type __tegra_cpu_reset_handler_data, %object .globl __tegra_cpu_reset_handler_data + .globl __tegra_cpu_reset_handler_data_offset + .equ __tegra_cpu_reset_handler_data_offset, \ + . - __tegra_cpu_reset_handler_start __tegra_cpu_reset_handler_data: - .rept TEGRA_RESET_DATA_SIZE - .long 0 + .rept TEGRA_RESET_DATA_SIZE + .long 0 .endr - .globl __tegra20_cpu1_resettable_status_offset - .equ __tegra20_cpu1_resettable_status_offset, \ - . - __tegra_cpu_reset_handler_start - .byte 0 .align L1_CACHE_SHIFT ENTRY(__tegra_cpu_reset_handler_end) diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index dc558892753c..b02ae7699842 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "iomap.h" #include "irammap.h" @@ -89,6 +90,8 @@ static void __init tegra_cpu_reset_handler_enable(void) void __init tegra_cpu_reset_handler_init(void) { + __tegra_cpu_reset_handler_data[TEGRA_RESET_TF_PRESENT] = + trusted_foundations_registered(); #ifdef CONFIG_SMP __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] = diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h index 9c479c7925b8..db0e6b3097ab 100644 --- a/arch/arm/mach-tegra/reset.h +++ b/arch/arm/mach-tegra/reset.h @@ -25,7 +25,11 @@ #define TEGRA_RESET_STARTUP_SECONDARY 3 #define TEGRA_RESET_STARTUP_LP2 4 #define TEGRA_RESET_STARTUP_LP1 5 -#define TEGRA_RESET_DATA_SIZE 6 +#define TEGRA_RESET_RESETTABLE_STATUS 6 +#define TEGRA_RESET_TF_PRESENT 7 +#define TEGRA_RESET_DATA_SIZE 8 + +#define RESET_DATA(x) ((TEGRA_RESET_##x)*4) #ifndef __ASSEMBLY__ @@ -49,7 +53,8 @@ void __tegra_cpu_reset_handler_end(void); (u32)__tegra_cpu_reset_handler_start))) #define tegra20_cpu1_resettable_status \ (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ - (u32)__tegra20_cpu1_resettable_status_offset)) + ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_RESETTABLE_STATUS] - \ + (u32)__tegra_cpu_reset_handler_start))) #endif #define tegra_cpu_reset_handler_offset \ diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index dedeebfccc55..50d51d3465f6 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -28,6 +28,7 @@ #include #include "irammap.h" +#include "reset.h" #include "sleep.h" #define EMC_CFG 0xc @@ -53,6 +54,9 @@ #define APB_MISC_XM2CFGCPADCTRL2 0x8e4 #define APB_MISC_XM2CFGDPADCTRL2 0x8e8 +#define __tegra20_cpu1_resettable_status_offset \ + (__tegra_cpu_reset_handler_data_offset + RESET_DATA(RESETTABLE_STATUS)) + .macro pll_enable, rd, r_car_base, pll_base ldr \rd, [\r_car_base, #\pll_base] tst \rd, #(1 << 30) -- 2.20.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C40FC43381 for ; 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[91.79.175.49]) by smtp.gmail.com with ESMTPSA id j12sm721202lfg.47.2019.02.22.10.04.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 22 Feb 2019 10:04:34 -0800 (PST) From: Dmitry Osipenko To: Russell King , Thierry Reding , Jonathan Hunter , Robert Yang , =?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?= Subject: [PATCH v5 5/8] ARM: tegra: Don't apply CPU erratas in insecure mode Date: Fri, 22 Feb 2019 20:59:23 +0300 Message-Id: <20190222175926.23366-6-digetx@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190222175926.23366-1-digetx@gmail.com> References: <20190222175926.23366-1-digetx@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190222_100436_738110_2789AF86 X-CRM114-Status: GOOD ( 14.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: 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CiBhcmNoL2FybS9tYWNoLXRlZ3JhL3NsZWVwLXRlZ3JhMjAuUyB8ICA0ICsrKysKIDQgZmlsZXMg Y2hhbmdlZCwgMjYgaW5zZXJ0aW9ucygrKSwgMTMgZGVsZXRpb25zKC0pCgpkaWZmIC0tZ2l0IGEv YXJjaC9hcm0vbWFjaC10ZWdyYS9yZXNldC1oYW5kbGVyLlMgYi9hcmNoL2FybS9tYWNoLXRlZ3Jh L3Jlc2V0LWhhbmRsZXIuUwppbmRleCA4MDVmMzA2ZmE2ZjcuLjZiZWE5NWQxNjVmYSAxMDA2NDQK LS0tIGEvYXJjaC9hcm0vbWFjaC10ZWdyYS9yZXNldC1oYW5kbGVyLlMKKysrIGIvYXJjaC9hcm0v bWFjaC10ZWdyYS9yZXNldC1oYW5kbGVyLlMKQEAgLTI5LDggKzI5LDYgQEAKIAogI2RlZmluZSBQ TUNfU0NSQVRDSDQxCTB4MTQwCiAKLSNkZWZpbmUgUkVTRVRfREFUQSh4KQkoKFRFR1JBX1JFU0VU XyMjeCkqNCkKLQogI2lmZGVmIENPTkZJR19QTV9TTEVFUAogLyoKICAqCXRlZ3JhX3Jlc3VtZQpA QCAtMTIxLDYgKzExOSwxMiBAQCBFTlRSWShfX3RlZ3JhX2NwdV9yZXNldF9oYW5kbGVyKQogCWNw c2lkCWFpZiwgMHgxMwkJCUAgU1ZDIG1vZGUsIGludGVycnVwdHMgZGlzYWJsZWQKIAogCXRlZ3Jh X2dldF9zb2NfaWQgVEVHUkFfQVBCX01JU0NfQkFTRSwgcjYKKworCWFkcglyMTIsIF9fdGVncmFf Y3B1X3Jlc2V0X2hhbmRsZXJfZGF0YQorCWxkcglyNSwgW3IxMiwgI1JFU0VUX0RBVEEoVEZfUFJF U0VOVCldCisJY21wCXI1LCAjMAorCWJuZQlhZnRlcl9lcnJhdGEKKwogI2lmZGVmIENPTkZJR19B UkNIX1RFR1JBXzJ4X1NPQwogdDIwX2NoZWNrOgogCWNtcAlyNiwgI1RFR1JBMjAKQEAgLTE1NSw3 ICsxNTksNiBAQCBhZnRlcl9lcnJhdGE6CiAJYW5kCXIxMCwgcjEwLCAjMHgzCQkJQCBSMTAgPSBD UFUgbnVtYmVyCiAJbW92CXIxMSwgIzEKIAltb3YJcjExLCByMTEsIGxzbCByMTAgIAkJQCBSMTEg PSBDUFUgbWFzawotCWFkcglyMTIsIF9fdGVncmFfY3B1X3Jlc2V0X2hhbmRsZXJfZGF0YQogCiAj aWZkZWYgQ09ORklHX1NNUAogCS8qIERvZXMgdGhlIE9TIGtub3cgYWJvdXQgdGhpcyBDUFU/ICov CkBAIC0xNjksMTAgKzE3Miw5IEBAIGFmdGVyX2VycmF0YToKIAljbXAJcjYsICNURUdSQTIwCiAJ Ym5lCTFmCiAJLyogSWYgbm90IENQVTAsIGRvbid0IGxldCBDUFUwIHJlc2V0IENQVTEgbm93IHRo YXQgQ1BVMSBpcyBjb21pbmcgdXAuICovCi0JbW92MzIJcjUsIFRFR1JBX0lSQU1fQkFTRSArIFRF R1JBX0lSQU1fUkVTRVRfSEFORExFUl9PRkZTRVQKIAltb3YJcjAsICNDUFVfTk9UX1JFU0VUVEFC TEUKIAljbXAJcjEwLCAjMAotCXN0cm5lYglyMCwgW3I1LCAjX190ZWdyYTIwX2NwdTFfcmVzZXR0 YWJsZV9zdGF0dXNfb2Zmc2V0XQorCXN0cm5lYglyMCwgW3IxMiwgI1JFU0VUX0RBVEEoUkVTRVRU QUJMRV9TVEFUVVMpXQogMToKICNlbmRpZgogCkBAIC0yNzcsMTQgKzI3OSwxMyBAQCBFTkRQUk9D KF9fdGVncmFfY3B1X3Jlc2V0X2hhbmRsZXIpCiAJLmFsaWduIEwxX0NBQ0hFX1NISUZUCiAJLnR5 cGUJX190ZWdyYV9jcHVfcmVzZXRfaGFuZGxlcl9kYXRhLCAlb2JqZWN0CiAJLmdsb2JsCV9fdGVn cmFfY3B1X3Jlc2V0X2hhbmRsZXJfZGF0YQorCS5nbG9ibAlfX3RlZ3JhX2NwdV9yZXNldF9oYW5k bGVyX2RhdGFfb2Zmc2V0CisJLmVxdQlfX3RlZ3JhX2NwdV9yZXNldF9oYW5kbGVyX2RhdGFfb2Zm c2V0LCBcCisJCQkJCS4gLSBfX3RlZ3JhX2NwdV9yZXNldF9oYW5kbGVyX3N0YXJ0CiBfX3RlZ3Jh X2NwdV9yZXNldF9oYW5kbGVyX2RhdGE6Ci0JLnJlcHQJVEVHUkFfUkVTRVRfREFUQV9TSVpFCi0J LmxvbmcJMAorCS5yZXB0ICAgVEVHUkFfUkVTRVRfREFUQV9TSVpFCisJLmxvbmcgICAwCiAJLmVu ZHIKLQkuZ2xvYmwJX190ZWdyYTIwX2NwdTFfcmVzZXR0YWJsZV9zdGF0dXNfb2Zmc2V0Ci0JLmVx dQlfX3RlZ3JhMjBfY3B1MV9yZXNldHRhYmxlX3N0YXR1c19vZmZzZXQsIFwKLQkJCQkJLiAtIF9f dGVncmFfY3B1X3Jlc2V0X2hhbmRsZXJfc3RhcnQKLQkuYnl0ZQkwCiAJLmFsaWduIEwxX0NBQ0hF X1NISUZUCiAKIEVOVFJZKF9fdGVncmFfY3B1X3Jlc2V0X2hhbmRsZXJfZW5kKQpkaWZmIC0tZ2l0 IGEvYXJjaC9hcm0vbWFjaC10ZWdyYS9yZXNldC5jIGIvYXJjaC9hcm0vbWFjaC10ZWdyYS9yZXNl dC5jCmluZGV4IGRjNTU4ODkyNzUzYy4uYjAyYWU3Njk5ODQyIDEwMDY0NAotLS0gYS9hcmNoL2Fy bS9tYWNoLXRlZ3JhL3Jlc2V0LmMKKysrIGIvYXJjaC9hcm0vbWFjaC10ZWdyYS9yZXNldC5jCkBA IC0yNCw2ICsyNCw3IEBACiAjaW5jbHVkZSA8YXNtL2NhY2hlZmx1c2guaD4KICNpbmNsdWRlIDxh c20vZmlybXdhcmUuaD4KICNpbmNsdWRlIDxhc20vaGFyZHdhcmUvY2FjaGUtbDJ4MC5oPgorI2lu Y2x1ZGUgPGFzbS90cnVzdGVkX2ZvdW5kYXRpb25zLmg+CiAKICNpbmNsdWRlICJpb21hcC5oIgog I2luY2x1ZGUgImlyYW1tYXAuaCIKQEAgLTg5LDYgKzkwLDggQEAgc3RhdGljIHZvaWQgX19pbml0 IHRlZ3JhX2NwdV9yZXNldF9oYW5kbGVyX2VuYWJsZSh2b2lkKQogCiB2b2lkIF9faW5pdCB0ZWdy YV9jcHVfcmVzZXRfaGFuZGxlcl9pbml0KHZvaWQpCiB7CisJX190ZWdyYV9jcHVfcmVzZXRfaGFu ZGxlcl9kYXRhW1RFR1JBX1JFU0VUX1RGX1BSRVNFTlRdID0KKwkJdHJ1c3RlZF9mb3VuZGF0aW9u c19yZWdpc3RlcmVkKCk7CiAKICNpZmRlZiBDT05GSUdfU01QCiAJX190ZWdyYV9jcHVfcmVzZXRf aGFuZGxlcl9kYXRhW1RFR1JBX1JFU0VUX01BU0tfUFJFU0VOVF0gPQpkaWZmIC0tZ2l0IGEvYXJj aC9hcm0vbWFjaC10ZWdyYS9yZXNldC5oIGIvYXJjaC9hcm0vbWFjaC10ZWdyYS9yZXNldC5oCmlu ZGV4IDljNDc5Yzc5MjViOC4uZGIwZTZiMzA5N2FiIDEwMDY0NAotLS0gYS9hcmNoL2FybS9tYWNo LXRlZ3JhL3Jlc2V0LmgKKysrIGIvYXJjaC9hcm0vbWFjaC10ZWdyYS9yZXNldC5oCkBAIC0yNSw3 ICsyNSwxMSBAQAogI2RlZmluZSBURUdSQV9SRVNFVF9TVEFSVFVQX1NFQ09OREFSWQkzCiAjZGVm aW5lIFRFR1JBX1JFU0VUX1NUQVJUVVBfTFAyCQk0CiAjZGVmaW5lIFRFR1JBX1JFU0VUX1NUQVJU VVBfTFAxCQk1Ci0jZGVmaW5lIFRFR1JBX1JFU0VUX0RBVEFfU0laRQkJNgorI2RlZmluZSBURUdS QV9SRVNFVF9SRVNFVFRBQkxFX1NUQVRVUwk2CisjZGVmaW5lIFRFR1JBX1JFU0VUX1RGX1BSRVNF TlQJCTcKKyNkZWZpbmUgVEVHUkFfUkVTRVRfREFUQV9TSVpFCQk4CisKKyNkZWZpbmUgUkVTRVRf REFUQSh4KQkoKFRFR1JBX1JFU0VUXyMjeCkqNCkKIAogI2lmbmRlZiBfX0FTU0VNQkxZX18KIApA QCAtNDksNyArNTMsOCBAQCB2b2lkIF9fdGVncmFfY3B1X3Jlc2V0X2hhbmRsZXJfZW5kKHZvaWQp OwogCSAodTMyKV9fdGVncmFfY3B1X3Jlc2V0X2hhbmRsZXJfc3RhcnQpKSkKICNkZWZpbmUgdGVn cmEyMF9jcHUxX3Jlc2V0dGFibGVfc3RhdHVzIFwKIAkoSU9fQUREUkVTUyhURUdSQV9JUkFNX0JB U0UgKyBURUdSQV9JUkFNX1JFU0VUX0hBTkRMRVJfT0ZGU0VUICsgXAotCSAodTMyKV9fdGVncmEy MF9jcHUxX3Jlc2V0dGFibGVfc3RhdHVzX29mZnNldCkpCisJKCh1MzIpJl9fdGVncmFfY3B1X3Jl c2V0X2hhbmRsZXJfZGF0YVtURUdSQV9SRVNFVF9SRVNFVFRBQkxFX1NUQVRVU10gLSBcCisJICh1 MzIpX190ZWdyYV9jcHVfcmVzZXRfaGFuZGxlcl9zdGFydCkpKQogI2VuZGlmCiAKICNkZWZpbmUg dGVncmFfY3B1X3Jlc2V0X2hhbmRsZXJfb2Zmc2V0IFwKZGlmZiAtLWdpdCBhL2FyY2gvYXJtL21h Y2gtdGVncmEvc2xlZXAtdGVncmEyMC5TIGIvYXJjaC9hcm0vbWFjaC10ZWdyYS9zbGVlcC10ZWdy YTIwLlMKaW5kZXggZGVkZWViZmNjYzU1Li41MGQ1MWQzNDY1ZjYgMTAwNjQ0Ci0tLSBhL2FyY2gv YXJtL21hY2gtdGVncmEvc2xlZXAtdGVncmEyMC5TCisrKyBiL2FyY2gvYXJtL21hY2gtdGVncmEv c2xlZXAtdGVncmEyMC5TCkBAIC0yOCw2ICsyOCw3IEBACiAjaW5jbHVkZSA8YXNtL2NhY2hlLmg+ CiAKICNpbmNsdWRlICJpcmFtbWFwLmgiCisjaW5jbHVkZSAicmVzZXQuaCIKICNpbmNsdWRlICJz bGVlcC5oIgogCiAjZGVmaW5lIEVNQ19DRkcJCQkJMHhjCkBAIC01Myw2ICs1NCw5IEBACiAjZGVm aW5lIEFQQl9NSVNDX1hNMkNGR0NQQURDVFJMMgkweDhlNAogI2RlZmluZSBBUEJfTUlTQ19YTTJD RkdEUEFEQ1RSTDIJMHg4ZTgKIAorI2RlZmluZSBfX3RlZ3JhMjBfY3B1MV9yZXNldHRhYmxlX3N0 YXR1c19vZmZzZXQgXAorCShfX3RlZ3JhX2NwdV9yZXNldF9oYW5kbGVyX2RhdGFfb2Zmc2V0ICsg UkVTRVRfREFUQShSRVNFVFRBQkxFX1NUQVRVUykpCisKIC5tYWNybyBwbGxfZW5hYmxlLCByZCwg cl9jYXJfYmFzZSwgcGxsX2Jhc2UKIAlsZHIJXHJkLCBbXHJfY2FyX2Jhc2UsICNccGxsX2Jhc2Vd CiAJdHN0CVxyZCwgIygxIDw8IDMwKQotLSAKMi4yMC4xCgoKX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX18KbGludXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxpc3QK bGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRl YWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAo=