From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v3 3/3] drm/i915: use REG_FIELD_PREP() to define register bitfield values Date: Wed, 27 Feb 2019 23:11:59 +0200 Message-ID: <20190227211159.GB20097@intel.com> References: <3f787052750840935689ac2fa8f3fa44cfbf1119.1551286447.git.jani.nikula@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7B04C6E134 for ; Wed, 27 Feb 2019 21:12:03 +0000 (UTC) Content-Disposition: inline In-Reply-To: <3f787052750840935689ac2fa8f3fa44cfbf1119.1551286447.git.jani.nikula@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org T24gV2VkLCBGZWIgMjcsIDIwMTkgYXQgMDc6MDI6MzhQTSArMDIwMCwgSmFuaSBOaWt1bGEgd3Jv dGU6Cj4gU2xpZ2h0bHkgdmVyYm9zZSwgYnV0IGRvZXMgYXdheSB3aXRoIGhhbmQgcm9sbGVkIHNo aWZ0cy4gVGllcyB0aGUgZmllbGQKPiB2YWx1ZXMgd2l0aCB0aGUgbWFzayBkZWZpbmluZyB0aGUg ZmllbGQuCj4gCj4gVW5mb3J0dW5hdGVseSB3ZSBoYXZlIHRvIG1ha2UgYSBsb2NhbCBjb3B5IG9m IEZJRUxEX1BSRVAoKSB0byBldmFsdWF0ZQo+IHRvIGEgaW50ZWdlciBjb25zdGFudCBleHByZXNz aW9uLiBCdXQgd2l0aCB0aGlzLCB3ZSBjYW4gZW5zdXJlIHRoZSBtYXNrCj4gaXMgbm9uLXplcm8s IHBvd2VyIG9mIDIsIGZpdHMgdTMyLCBhbmQgdGhlIHZhbHVlIGZpdHMgdGhlIG1hc2sgKHdoZW4g dGhlCj4gdmFsdWUgaXMgYSBjb25zdGFudCBleHByZXNzaW9uKS4KCkkgbWlnaHQgbGlrZSBhIGRl YnVnIGtub2IgdG8gbWFrZSB0aGF0IGludG8gYSBydW50aW1lIGNoZWNrIGZvcgpub24tY29uc3Qg ZXhwcmVzc2lvbnMuIEJ1dCB0aGF0IGNhbiBiZSBjb25zaWRlcmVkIGxhdGVyLgoKLS0gClZpbGxl IFN5cmrDpGzDpApJbnRlbApfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fXwpJbnRlbC1nZnggbWFpbGluZyBsaXN0CkludGVsLWdmeEBsaXN0cy5mcmVlZGVza3Rv cC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRl bC1nZng=