From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v3 1/3] drm/i915: introduce REG_BIT() and REG_GENMASK() to define register contents Date: Wed, 27 Feb 2019 23:13:46 +0200 Message-ID: <20190227211346.GC20097@intel.com> References: <5bd0d22ae0a0a3d7500e63ec80073c2f476faecb.1551286447.git.jani.nikula@intel.com> <155130063122.5847.606684084113121815@skylake-alporthouse-com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id D07496E135 for ; Wed, 27 Feb 2019 21:13:50 +0000 (UTC) Content-Disposition: inline In-Reply-To: <155130063122.5847.606684084113121815@skylake-alporthouse-com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Chris Wilson Cc: Jani Nikula , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org T24gV2VkLCBGZWIgMjcsIDIwMTkgYXQgMDg6NTA6MzFQTSArMDAwMCwgQ2hyaXMgV2lsc29uIHdy b3RlOgo+IFF1b3RpbmcgSmFuaSBOaWt1bGEgKDIwMTktMDItMjcgMTc6MDI6MzYpCjxzbmlwPgo+ ID4gICNkZWZpbmUgIFBQX1JFRkVSRU5DRV9ESVZJREVSX1NISUZUICAgIDgKPiA+IC0jZGVmaW5l ICBQQU5FTF9QT1dFUl9DWUNMRV9ERUxBWV9NQVNLICAweDFmCj4gPiArI2RlZmluZSAgUEFORUxf UE9XRVJfQ1lDTEVfREVMQVlfTUFTSyAgUkVHX0dFTk1BU0soNCwgMCkKPiAKPiBPay4KPiAKPiBJ J2xsIGdldCB1c2VkIHRvIHRoZSBoaSxsbyBjb252ZW50aW9uIGV2ZW50dWFsbHkuCgpUaGUgbmlj ZSB0aGluZyBpcyB0aGF0IGl0IG1hdGNoZXMgdGhlIHNwZWMuCgpUaGUgaGFyZCBwYXJ0IGlzIHJ1 bm5pbmcgb3V0IG9mIGZpbmdlcnMgZm9yIHdpZGUgYml0ZmllbGRzIDpQCgotLSAKVmlsbGUgU3ly asOkbMOkCkludGVsCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fCkludGVsLWdmeCBtYWlsaW5nIGxpc3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9y ZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVsLWdm eA==