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From: David Hildenbrand <david@redhat.com>
To: qemu-devel@nongnu.org
Cc: qemu-s390x@nongnu.org, "Thomas Huth" <thuth@redhat.com>,
	"Cornelia Huck" <cohuck@redhat.com>,
	"Richard Henderson" <rth@twiddle.net>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"David Hildenbrand" <david@redhat.com>
Subject: [Qemu-devel] [PATCH RFC2 2/2] tests/tcg: target/s390x: Test VECTOR LOAD GR FROM VR ELEMENT
Date: Wed, 27 Feb 2019 22:15:25 +0100	[thread overview]
Message-ID: <20190227211525.2470-3-david@redhat.com> (raw)
In-Reply-To: <20190227211525.2470-1-david@redhat.com>

Reuse the existing helpers.

Signed-off-by: David Hildenbrand <david@redhat.com>
---
 tests/tcg/s390x/Makefile.target |  1 +
 tests/tcg/s390x/helper.h        |  6 ++++++
 tests/tcg/s390x/vlgv.c          | 37 +++++++++++++++++++++++++++++++++
 3 files changed, 44 insertions(+)
 create mode 100644 tests/tcg/s390x/vlgv.c

diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.target
index 474c2428bd..deffc4c525 100644
--- a/tests/tcg/s390x/Makefile.target
+++ b/tests/tcg/s390x/Makefile.target
@@ -8,6 +8,7 @@ TESTS+=exrl-trtr
 TESTS+=pack
 
 VECTOR_TESTS=vge
+VECTOR_TESTS+=vlgv
 TESTS+=$(VECTOR_TESTS)
 
 #enable vectors and optimisation for vector tests
diff --git a/tests/tcg/s390x/helper.h b/tests/tcg/s390x/helper.h
index ecbd97519b..790ced7ad7 100644
--- a/tests/tcg/s390x/helper.h
+++ b/tests/tcg/s390x/helper.h
@@ -11,6 +11,12 @@ typedef union S390Vector {
     uint8_t h[16];
 } S390Vector;
 
+#define ES_8    0
+#define ES_16   1
+#define ES_32   2
+#define ES_64   3
+#define ES_128  4
+
 static inline void check(const char *s, bool cond)
 {
     if (!cond) {
diff --git a/tests/tcg/s390x/vlgv.c b/tests/tcg/s390x/vlgv.c
new file mode 100644
index 0000000000..2a4cca3bbb
--- /dev/null
+++ b/tests/tcg/s390x/vlgv.c
@@ -0,0 +1,37 @@
+#include <stdint.h>
+#include <unistd.h>
+#include "signal-helper.inc.c"
+
+static inline void vlgv(uint64_t *r1, S390Vector *v3, const void *a2,
+                        uint8_t m4)
+{
+    asm volatile("vlgv %[r1], %[v3], 0(%[a2]), %[m4]\n"
+                 : [r1] "+d" (*r1),
+                   [v3] "+v" (v3->v)
+                 : [a2] "d" (a2),
+                   [m4] "i" (m4));
+}
+
+int main(void)
+{
+    S390Vector v3 = {
+        .q[0] = 0x0011223344556677ull,
+        .q[1] = 0x8899aabbccddeeffull,
+    };
+    uint64_t r1 = 0;
+
+    /* Directly set all ignored bits to  */
+    vlgv(&r1, &v3, (void *)(7 | ~0xf), ES_8);
+    check("8 bit", r1 == 0x77);
+    vlgv(&r1, &v3, (void *)(4 | ~0x7), ES_16);
+    check("16 bit", r1 == 0x8899);
+    vlgv(&r1, &v3, (void *)(3 | ~0x3), ES_32);
+    check("32 bit", r1 == 0xccddeeff);
+    vlgv(&r1, &v3, (void *)(1 | ~0x1), ES_64);
+    check("64 bit", r1 == 0x8899aabbccddeeffull);
+    check("v3 not modified", v3.q[0] == 0x0011223344556677ull &&
+                             v3.q[1] == 0x8899aabbccddeeffull);
+
+    CHECK_SIGILL(vlgv(&r1, &v3, NULL, ES_128));
+    return 0;
+}
-- 
2.17.2

  parent reply	other threads:[~2019-02-27 21:15 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-27 21:15 [Qemu-devel] [PATCH RFCv2 0/2] tests/tcg: Vector instruction tests for target/s390x David Hildenbrand
2019-02-27 21:15 ` [Qemu-devel] [PATCH RFC2 1/2] tests/tcg: target/s390x: Test VECTOR GATHER ELEMENT David Hildenbrand
2019-02-28  7:22   ` David Hildenbrand
2019-02-27 21:15 ` David Hildenbrand [this message]
2019-02-27 21:23 ` [Qemu-devel] [PATCH RFCv2 0/2] tests/tcg: Vector instruction tests for target/s390x no-reply

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